Principal SoC Design Engineer
About the role
Arm's Solution Engineering division is seeking a Principal SoC Design Engineer in San Diego to contribute to the specification, design, and verification of complex compute subsystems and SoCs. The role focuses on developing logic and micro-architecture specifications for high-performance compute and AI solutions using IP products from Arm and other vendors.
What you'll do
- Review SoC architecture and develop micro-architecture specifications to meet complex power and performance goals.
- Develop RTL using Verilog HDL, resolve bugs, run static design checks, and contribute to implementation constraints generation.
- Collaborate with verification teams to review test plans and debug design issues, and partner with power and performance analysis teams to optimize SoCs.
- Contribute to developing and enhancing internal design methodologies across the engineering team.
- Mentor and support team members to drive project completion, while coordinating with project management on plans and schedules.
What you'll need
- Bachelor's or Master's degree in Computer Science, Electrical Engineering, Computer Engineering, or a related field.
- 10+ years of experience in the design of complex compute subsystems or SoCs.
- Experience in digital hardware design for complex systems using Verilog HDL.
- Experience with power and clock domain crossing, alongside static design checks such as linting, CDC/RDC, and X-propagation.
- Experience or knowledge in synthesis, timing constraints, and power management techniques.
- Experience collaborating with verification teams on design quality closure.
- Scripting experience with Perl, Python, or related languages.
- Leadership, mentoring, or coaching experience.
Nice to have
- Experience with ARM-based designs or ARM System Architectures.
- Experience with SystemVerilog and verification methodologies such as UVM, OVM, or e.
- Experience with UPF and IP-XACT.
- Experience leading teams or projects.
- Experience developing and integrating subsystems for PCIe, UCIe, DDR/LPDDR/HBM, or Ethernet.
- Understanding of DFT concepts including RTL testability, scan insertion, and OCC.
Skills: Verilog HDL, power and clock domain crossing, linting, CDC/RDC, X-propagation, synthesis, timing constraints
More semiconductor jobs: Arm Holdings jobs · RTL design jobs · San Diego jobs
This role has been open 100 days — well above the 64-day median for Digital/RTL Design roles.
Digital/RTL Design · RTL Design
|
Open roles in category
1096
|
Median days open
64 d
|
Category median salary (all employers)
$189k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Arm Holdings | All employers we track in this specialty (1096 roles · 104 employers) |
|---|---|---|
| Open roles in this specialty | 30 | 1096 |
| Open roles in the wider Digital Design & Verification family | 127 | 3525 · 120 employers |
| Median days open | 11 d | 64 d (−53 d vs this employer) |
| Median salary (USD postings) | — | $189k |
Skills observed across this category: Verilog HDL, power and clock domain crossing, linting, CDC/RDC, X-propagation, synthesis
Who's hiring in this category
- Qualcomm · 139 open roles · median 73 d
- AMD · 94 open roles · median 50 d
- Synopsys · 90 open roles · median 51 d
- NVIDIA · 47 open roles · median 64 d
- NXP Semiconductors · 45 open roles · median 107 d
- Analog Devices · 41 open roles · median 54 d
How we counted: 1096 open Digital/RTL Design (RTL Design) roles from 104 employers tracked in the SemiconductorJobs index, counted 8 Nov 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.