Principal SoC Architect (ML Accelerators) - Austin, Texas, United States
Originally posted 6 February 2026 by the employer.
About the role
As a Principal SoC Architect (ML Accelerators), you will define the architectures and design tradeoffs of ML-centric SoCs that fuse analog precision, digital signal processing, and embedded machine learning. You will guide design principles for custom accelerators, memory hierarchies, and SoC fabrics optimized for voice/image, sense, and control domains.
What you'll do
- Define the end-to-end architecture for ML accelerators and SoCs, including compute fabrics, dataflows, memory hierarchies, and mixed-signal front-end integration. - Lead architectural exploration of performance, power, area, and cost tradeoffs using workload-driven models and benchmarks. - Collaborate on ISA and compiler/toolchain co-design to optimize micro-architecture and runtime stacks for ML workloads and domain-specific kernels. - Prototype candidate architectures on FPGA and ASIC platforms with internal teams, startups, and research partners. - Define on-chip security architectures, including trusted execution environments (TEE), enclaves, memory partitioning, and hardware root-of-trust. - Evaluate external IP, startups, and academic research in ML accelerators for licensing, incubation, and partnerships.
What you'll need
- Ph.D. or Master’s degree in Electrical Engineering, Computer Engineering, or a related technical field. - 10+ years of experience in SoC or accelerator design, focused on ML, DSP, or edge compute. - Technical understanding of ML accelerator architectures, including systolic arrays, SIMD/VLIW, RISC-V/ARM integration, memory subsystems, and dataflow optimization. - Hands-on experience defining ISAs or ISA extensions and collaborating with compiler and runtime teams. - Experience in architectural modeling, workload benchmarking, and system-level tradeoff analysis. - Experience with simulation, emulation, FPGA prototyping, and performance modeling frameworks.
Nice to have
- Experience in hardware-level security stacks, including TEEs, enclaves, memory isolation schemes, secure boot, and cryptographic accelerators. - Experience driving early-stage architectural concepts through exploration to prototype within startup or incubator environments. - Expertise in energy-efficient architectures and low-power design for edge workloads. - Strong network in academia and industry across ML accelerators, SoC design, or edge AI. - Demonstrated IP generation and publications in conferences or journals. - Familiarity with agile practices for rapid prototyping and early product validation.
Skills: ML accelerators, SoC architecture, memory hierarchies, ISA & Compiler Co-Design, security architecture
This role has been open 220 days — well above the 88-day median for AI/ML Hardware Engineering roles.
AI/ML Hardware Engineering · AI ML Hardware
|
Open roles in category
504
|
Median days open
88 d
|
Median salary
$236k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Cirrus Logic | All employers we track in this specialty (504 roles · 77 employers) |
|---|---|---|
| Open roles in this specialty | 1 | 504 |
| Open roles in the wider Software, Firmware & Systems family | 14 | 6302 · 146 employers |
| Median days open | 220 d | 88 d (+132 d vs this employer) |
| Median salary (USD postings) | — | $236k |
Skills observed across this category: ML accelerators, SoC architecture, memory hierarchies, ISA & Compiler Co-Design, security architecture
Who's hiring in this category
- Qualcomm · 104 open roles · median 117 d
- NVIDIA · 88 open roles · median 59 d
- AMD · 33 open roles · median 108 d
- Micron Technology · 26 open roles · median 60 d
- Mobileye · 20 open roles · median 87 d
- Analog Devices · 18 open roles · median 44 d
How we counted: 504 open AI/ML Hardware Engineering (AI ML Hardware) roles from 77 employers tracked in the SemiconductorJobs index, counted 26 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Software, Firmware & Systems family row. Figures refresh nightly.