Principal, SMTS, DRAM Systems Architect - Boise, ID - Main Site, United States

Originally posted 22 July 2026 by the employer — open 50 days.

This role contributes to the development of critical high-speed IP circuits used across Micron’s DRAM memory products.

About the role

This role is for a Principal/Sr Member of Technical Staff (SMTS) in high-speed IO/Clocking Design Engineering, contributing to the development of critical high-speed IP circuits for Micron’s DRAM memory products.

What you'll do

• Define, innovate, design, optimize, and verify high-speed IO and clocking circuits used in new DRAM products.
• Apply robust high-speed circuit design techniques and enhance critical performance evaluation, including timing and jitter sensitivity, of the IO data path and clock path.
• Develop accurate modeling, analysis, and simulation methodology to capture key circuit performance metrics.
• Work with Product Engineering and SI team to compare silicon performance with simulation results and support correlation activities.
• Collaborate with process integration and transistor modeling teams on Micron's process node.

What you'll need

• MSEE + 10 years or BSEE + 12 years of industry experience with strong background in designing high-speed IO interface, timing and clocking circuits with proven silicon successes.
• Ability to supervise layout work and understand good layout practices for high-speed circuits to minimize parasitic impacts.

Nice to have

• Prior experience in DRAM circuit design.
• Prior experience in channel modeling and characterization, transceiver noise and timing budget analysis, and equalization techniques.
• Understanding of device physics and basic CMOS processing techniques.
• Demonstrated ability with AI/ML usage and fluency in scripting languages such as PERL/Python.

Skills: high-speed IO interface, clocking circuits, DRAM products, timing and jitter, channel modeling