Principal Signal Integrity Engineer
Analog & Mixed-Signal Design
This role focuses on 112G/224G SerDes and multi-chip modules (MCM).
About the role
This role is responsible for the electrical integrity of d-Matrix’s high-performance AI compute platforms, specifically pushing 112G/224G SerDes and delivering thousands of Amps to multi-chip modules (MCM).
What you'll do
- Lead the modeling and analysis of complex multi-chip packages, including interposer routing, micro-bump parasitic extraction, and die-to-die (D2D) link budgeting.
- Design and optimize the Power Delivery Network (PDN) to meet stringent Z_Target requirements and perform transient analysis.
- Perform comprehensive channel simulations (pre- and post-layout) using IBIS-AMI models and define jitter, crosstalk, and loss budgets for 112G+ channels.
- Lead the "Gold Suite" validation in the lab and correlate simulation results with VNA, TDR, and high-speed oscilloscope measurements.
- Translate complex simulation findings into actionable physical layout constraints for the PCB Design team, specifically for advanced stack-ups and high-density routing.
What you'll need
- MS/PhD in Electrical Engineering or a related field with a focus on Electromagnetics or Signal Integrity.
- 12+ years in SI/PI design for high-performance networking, GPUs, or server platforms.
- Expert-level proficiency in Ansys HFSS, Cadence Sigrity, Keysight ADS, or Simbeor.
- Expert-level proficiency in Ansys SIwave, Cadence PowerSI, or CST.
- Proven track record with 112G SerDes and high-speed memory architectures.
- Deep understanding of PAM4 signaling and FEC (Forward Error Correction) impact on link margins.
- Hands-on experience with 50GHz+ VNAs, TDRs, and real-time/sampling oscilloscopes.
Nice to have
- Knowledge of PCB Material Science (e.g., glass weave effects, skin effect loss, copper roughness modeling).
- Experience with Python or MATLAB for post-processing large simulation datasets and automating sweep analysis.
- Familiarity with OCP (Open Compute Project) hardware specifications for AI modules.
Skills: SI/PI, 112G/224G SerDes, MCM, PDN architecting, channel simulations, lab correlation
Market context
This role has been open 85 days — below the 89-day median for High-Speed IO/SerDes Design roles.
High-Speed IO/SerDes Design · Serdes Highspeed
|
Open roles in category
215
|
Median days open
89 d
|
Median salary
$184k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | d-Matrix | Market (215 open roles · 44 companies) |
|---|---|---|
| Open roles in category | 3 | 215 |
| Median days open | 21 d | 89 d (−68 d vs this employer) |
| Median salary (USD postings) | — | $184k |
Skills observed across this category: SI/PI, 112G/224G SerDes, MCM, PDN architecting, channel simulations, lab correlation
Who's hiring in this category
- AMD · 24 open roles · median 60 d
- Cadence Design Systems · 19 open roles · median 152 d
- Qualcomm · 18 open roles · median 68 d
- Synopsys · 16 open roles · median 52 d
- Broadcom · 11 open roles · median 141 d
- Micron Technology · 9 open roles · median 126 d
Based on 215 open roles at 44 companies in our index. Snapshot 9 Sept 2026.