Principal Signal and Power Integrity Engineer - San Jose, CA, United States
$203,000 USD yearly
Originally posted 25 February 2026 by the employer — open 197 days.
About the role
This role involves executing signal integrity (SI) and power integrity (PI) planning, design, modeling, simulation, and lab validation for connectivity products.
What you'll do
- Execute SI planning, design, modeling, simulation, and lab validation with various system configurations.
- Define hardware system constraints and high-speed technology roadmaps.
- Collaborate with the electrical design community to develop systems.
- Debug, analyze, and solve problems, leading root cause and corrective action teams.
What you'll need
- Bachelor's degree in electrical engineering.
- 8+ years of experience supporting or developing complex SoC/silicon products for Server and Networking applications.
- 8+ years of hands-on high-speed SI/PI design, simulation, and measurement experience.
- Familiarity with SI and PI design challenges for PCIe Gen5/6 and/or 224/448G Ethernet PCB and interconnects.
- Experience with 2D and 3D EM simulation using Cadence/Ansys/ADS/etc. toolsets.
- Experience with EM modeling of BGA and connector structures.
- High-speed SERDES channel simulation and equalization.
- Experience with PI simulations using Ansys/Cadence toolsets.
- Familiarity with VNA, TDR, real-time and sub-sampling oscilloscopes.
- Working knowledge of PCB fabrication limits and trade-offs.
- Familiarity with industry-standard such as PCI-SIG and IEEE802.3, especially Electrical sections.
Nice to have
- Master's degree in electrical engineering.
Skills: SI/PI design, simulation, lab validation, PCIe Gen5/6, 224/448G Ethernet
This role has been open 178 days — well above the 91-day median for High-Speed IO/SerDes Design roles.
High-Speed IO/SerDes Design · Serdes Highspeed
|
Open roles in category
217
|
Median days open
91 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Astera Labs | All employers we track in this specialty (217 roles · 44 employers) |
|---|---|---|
| Open roles in category | 4 | 217 |
| Median days open | 76 d | 91 d (−15 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: SI/PI design, simulation, lab validation, PCIe Gen5/6, 224/448G Ethernet
Who's hiring in this category
- AMD · 24 open roles · median 61 d
- Cadence Design Systems · 19 open roles · median 153 d
- Qualcomm · 17 open roles · median 74 d
- Synopsys · 16 open roles · median 53 d
- Broadcom · 11 open roles · median 142 d
- NVIDIA · 10 open roles · median 95 d
How we counted: 217 open High-Speed IO/SerDes Design (Serdes Highspeed) roles from 44 employers tracked in the SemiconductorJobs index, counted 10 Sept 2026. Figures refresh nightly.