Principal SI/PI Engineer - 18231
Originally posted 23 July 2026 by the employer.
About the role
This role involves developing and maintaining SerDes system models for PAM4 transceivers, focusing on PCIe (128Gbps+) and Ethernet (200Gbps+) standards.
What you'll do
- Develop and maintain SerDes system models for PAM4 transceivers targeting PCIe (128Gbps+) and Ethernet (200Gbps+) standards.
- Run comprehensive system simulations to verify and sign-off design performance across multiple protocols and channels.
- Design and propose advanced algorithms to calibrate and adapt transceivers for optimal performance.
- Correlate simulated performance with silicon measurements to ensure accuracy and reliability.
- Provide expert assistance to customers for system-level performance issues and troubleshooting.
- Collaborate with cross-functional teams of analog, digital, and hardware engineers throughout all stages of development and post-silicon.
What you'll need
- M.Sc. or Ph.D. in Electrical or Computer Engineering with 6 to 8+ years of relevant experience.
- Strong experience modeling circuits and systems in MATLAB/Simulink.
- Solid understanding of DSP and communications theory, including equalization, encoding, and noise/crosstalk filtering.
- Proficiency in analyzing link budgets for PAM4 high-speed serial links.
- Experience with wireline protocols (PCIe, Ethernet, JESD204C, CPRI) and optical protocols (LINEAR, RTLR).
- Experience with circuit topologies used in high-speed SerDes Tx/Rx and Tx/Rx equalization techniques.
- Hands-on lab testing for high-speed serial links and proficiency in C/Verilog-A/system Verilog.
Nice to have
- Programming in Python.
Skills: SerDes system models, PAM4 transceivers, PCIe, Ethernet, DSP
This role has been open 67 days — below the 76-day median for High-Speed IO/SerDes Design roles.
High-Speed IO/SerDes Design · Serdes Highspeed
|
Open roles in category
239
|
Median days open
76 d
|
Median salary
$177k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Synopsys | All employers we track in this specialty (239 roles · 49 employers) |
|---|---|---|
| Open roles in this specialty | 28 | 239 |
| Open roles in the wider Analog & Mixed-Signal family | 38 | 1385 · 108 employers |
| Median days open | 32 d | 76 d (−44 d vs this employer) |
| Median salary (USD postings) | — | $177k |
Skills observed across this category: SerDes system models, PAM4 transceivers, PCIe, Ethernet, DSP
Who's hiring in this category
- AMD · 28 open roles · median 64 d
- Synopsys (this employer) · 26 open roles · median 44 d
- Qualcomm · 20 open roles · median 58 d
- Cadence Design Systems · 18 open roles · median 181 d
- Apple · 12 open roles · median 7 d
- NVIDIA · 11 open roles · median 116 d
How we counted: 239 open High-Speed IO/SerDes Design (Serdes Highspeed) roles from 49 employers tracked in the SemiconductorJobs index, counted 30 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Analog & Mixed-Signal family row. Figures refresh nightly.