Principal Product Engineer - Austin, United States
Originally posted 17 September 2026 by the employer — open 0 days.
About the role
This role involves influencing the development of software tools for advanced chip design platforms within the Digital and Signoff Group. This position focuses on providing technical place and route expertise for Cadence products.
What you'll do
- Support Cadence products in the Digital and Signoff team.
- Track and debug customer issues and work with R&D and release team on issue resolution.
- Run design benchmarks and develop flows and solutions.
What you'll need
- MS in EE with 5+ years of experience in Digital Implementation (design engineer or product engineer) OR BS in EE with 8+ years of experience in Digital Implementation (design engineer or product engineer).
- Strong understanding of VLSI physical design and timing analysis.
- Familiarity with digital implementation challenges including RTL synthesis, placement optimization, clock tree synthesis, routing optimization, and silicon signoff.
- Experience with industry standard EDA tools in Synthesis, Physical design, and Signoff at 16nm and below nodes.
- Exposure to, and solid understanding of, hierarchical design methodologies and low power design.
- Automation skills using Perl, Tcl, and shell scripting.
Skills: software tools, advanced chip design platforms, place and route expertise, RTL to GDSII flow, timing closure, PPA optimization
This role has been open 0 days — well below the 86-day median for EDA/CAD Engineering roles.
EDA/CAD Engineering · EDA Tools
|
Open roles in category
680
|
Median days open
86 d
|
Median salary
$197k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Cadence Design Systems | All employers we track in this specialty (680 roles · 73 employers) |
|---|---|---|
| Open roles in this specialty | 168 | 680 |
| Open roles in the wider Physical Implementation family | 198 | 1379 · 105 employers |
| Median days open | 146 d | 86 d (+60 d vs this employer) |
| Median salary (USD postings) | — | $197k |
Skills observed across this category: software tools, advanced chip design platforms, place and route expertise, RTL to GDSII flow, timing closure, PPA optimization
Who's hiring in this category
- Cadence Design Systems (this employer) · 173 open roles · median 141 d
- Synopsys · 52 open roles · median 58 d
- NVIDIA · 50 open roles · median 90 d
- Micron Technology · 36 open roles · median 119 d
- Qualcomm · 36 open roles · median 72 d
- Intel Corporation · 29 open roles · median 23 d
How we counted: 680 open EDA/CAD Engineering (EDA Tools) roles from 73 employers tracked in the SemiconductorJobs index, counted 18 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Physical Implementation family row. Figures refresh nightly.