Principal PLL Design Engineer - Irvine, CA or San Jose, CA, United States

Originally posted 6 April 2026 by the employer.

About the role

As a PLL Design Engineer, you will architect and design PLLs for advanced transceiver technologies. This role involves working with clocking circuits for optical transceivers, high-speed SerDes, and ADC/DAC systems.

What you'll do

• Understand tradeoffs between PLL topologies (integer-N, fractional-N, all-digital/ADPLL) to meet specifications.
• Architect, design, and simulate analog/mixed-signal PLL building blocks (VCOs, charge pumps, dividers, PFDs, Loop Filters) at the transistor level.
• Address challenges in advanced node technologies, including self-heating, electromigration, VCO linearization, and device-level noise optimization.
• Supervise and verify layouts from layout engineers to ensure floorplanning, matching, and parasitic minimization.
• Be responsible for PLL bring-up in the lab and conduct performance characterization.
• Conduct system-level simulations and validation for PLL integration into advanced transceiver technologies.

What you'll need

• Master's or PhD in Electrical Engineering with 5+ years of relevant PLL design experience and production-level tape-out experience.
• Extensive experience with advanced node technologies (16nm/12nm, 7nm, 5nm, 3nm, 2nm processes).
• Deep understanding of phase noise analysis, VCO design, LDOs, and supporting circuitry associated with PLLs.
• Proficiency in Cadence Virtuoso, electromagnetic simulators (e.g., EMX/HFSS), and MATLAB for system-level modeling.

Nice to have

• Strong communication and documentation skills

Skills: PLL topologies, VCOs, Cadence Virtuoso, Spectre, transistor level