Principal Physical Verification Engineer - San Jose, CA, United States
$150,000 - $250,000 USD yearly
Originally posted 21 September 2026 by the employer.
Celero is developing 2nm coherent DSP silicon.
About the role
This role involves leading full-chip physical verification efforts for complex digital blocks and full-chip implementations. You will own all aspects of Physical Verification execution on advanced TSMC nodes.
What you'll do
- Lead full chip Physical Verification effort.
- Own execution plans and schedules for full-chip.
- Run and analyze DRC/ERC/LUP/PERC results.
- Partner with analog, block, and chip top owners to ensure clean floorplan.
- Influence floorplan constraints, hierarchy, and implementation strategy.
- Participate in tapeout readiness reviews.
What you'll need
- Bachelor’s or Master’s degree in Electrical Engineering or related field.
- 7+ years of experience with full-chip verifications.
- Hands-on experience with Physical Verification tools (Synopsys IC Validator (ICV), Siemens Calibre).
- Ability to assemble a flow to support block/chip level PV.
- Expertise in Floorplanning to avoid DRC/LVS issues.
- Ability to provide guidance to analog IP team to allow for clean integration.
Nice to have
- Experience in advanced technology nodes (7nm, 5nm, 3nm).
- Automation skills using Tcl, Python, or shell scripting.
Skills: full chip Physical Verification, DRC/ERC/LUP/PERC, ICV or Calibre, advanced technology nodes, floorplanning
This role has been open 0 days — well below the 61-day median for Physical Design roles.
Physical Design · Physical Design
|
Open roles in category
606
|
Median days open
61 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Celero | All employers we track in this specialty (606 roles · 78 employers) |
|---|---|---|
| Open roles in this specialty | 8 | 606 |
| Open roles in the wider Physical Implementation family | 8 | 1415 · 108 employers |
| Median days open | 18 d | 61 d (−43 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: full chip Physical Verification, DRC/ERC/LUP/PERC, ICV or Calibre, advanced technology nodes, floorplanning
Who's hiring in this category
- Qualcomm · 111 open roles · median 43 d
- Broadcom · 38 open roles · median 71 d
- NVIDIA · 38 open roles · median 46 d
- AMD · 35 open roles · median 41 d
- Synopsys · 27 open roles · median 60 d
- Renesas Electronics · 25 open roles · median 48 d
How we counted: 606 open Physical Design (Physical Design) roles from 78 employers tracked in the SemiconductorJobs index, counted 22 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Physical Implementation family row. Figures refresh nightly.