Principal Physical Design Engineer, STA - San Jose, California, United States
$209,000 - $250,000 USD yearly
Originally posted 20 May 2026 by the employer.
Drive block and full-chip STA closure on TSMC 7nm and below connectivity ASICs.
About the role
As a Principal Physical Design Engineer, STA, you will own planning, coordination, and execution of static timing analysis supporting connectivity ASICs from RTL through sign-off. The role requires end-to-end STA ownership across design stages, collaborating with RTL, physical design, and verification teams to ensure full-chip timing convergence.
What you'll do
- Drive timing closure from RTL through sign-off across complex SoCs. - Develop and validate SDC constraints, including MMMC setup, and define I/O timing budgets across hierarchical designs. - Apply sign-off methodologies at TSMC 7nm and below, accounting for OCV/AOCV and PVT effects. - Leverage ETM libraries for hierarchical timing analysis and correlation while balancing runtime and accuracy. - Manage large-scale multi-corner/multi-mode STA runs using automation, partitioning, and compute resource management. - Generate and validate timing ECOs, providing root cause analysis and guidance to physical design and RTL teams.
What you'll need
- Bachelor’s in Electrical Engineering or Computer Science. - ≥10 years of experience in timing analysis and sign-off for complex SoCs in Server, Storage, or Networking applications. - Expertise in timing constraints, STA methodology, and timing closure at block and full-chip levels. - Strong knowledge of synthesis, place-and-route, extraction, and equivalence checking flows in advanced nodes (7nm or below). - Proficiency with Cadence and/or Synopsys physical design and STA toolchains. - Strong scripting ability in Tcl, Python, or Perl.
Nice to have
- Familiarity with high-speed SerDes or Ethernet PHY timing challenges. - Knowledge of ECO methodologies, DFT tools, and test coverage analysis. - Experience working with IP vendors for RTL and hard-macro integration. - Familiarity with SystemVerilog/Verilog. - Master's degree in Electrical Engineering or Computer Science.
Skills: Timing closure, STA, SDC constraints, sign-off methodologies, ECO
This role has been open 156 days — well above the 64-day median for Physical Design roles.
Physical Design · Physical Design
|
Open roles in category
673
|
Median days open
64 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Astera Labs | All employers we track in this specialty (673 roles · 79 employers) |
|---|---|---|
| Open roles in this specialty | 18 | 673 |
| Open roles in the wider Physical Implementation family | 24 | 1489 · 109 employers |
| Median days open | 104 d | 64 d (+40 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: Timing closure, STA, SDC constraints, sign-off methodologies, ECO
Who's hiring in this category
- Qualcomm · 123 open roles · median 47 d
- AMD · 64 open roles · median 27 d
- Intel Corporation · 40 open roles · median 16 d
- Synopsys · 37 open roles · median 38 d
- NVIDIA · 36 open roles · median 66 d
- Broadcom · 34 open roles · median 103 d
How we counted: 673 open Physical Design (Physical Design) roles from 79 employers tracked in the SemiconductorJobs index, counted 24 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Physical Implementation family row. Figures refresh nightly.