Principal Physical Design Engineer - San Jose, California, United States
$135,000 - $195,000 USD yearly
Originally posted 31 March 2026 by the employer.
Own the full RTL2GDS implementation from synthesis to tapeout for AI connectivity SoCs on 7nm and below.
About the role
Astera Labs is looking for a Principal Physical Design Engineer to own the backend implementation of complex SoCs for rack-scale AI connectivity infrastructure. In this role, you will lead the implementation from RTL to tapeout on advanced process nodes, guiding floorplan, timing, power, and signoff strategies.
What you'll do
- Own the full RTL2GDS flow on advanced process nodes, including synthesis, floorplan, placement, CTS, routing, and signoff across connectivity products. - Drive block- and chip-level place & route strategy, congestion resolution, and routing convergence on high-frequency, high-density designs. - Architect clock tree synthesis and clocking topology to meet skew, latency, and power targets. - Lead tapeout execution, including final ECO closure, GDS handoff, and post-tapeout support through fab. - Drive multi-mode multi-corner STA closure, low-power implementation (UPF/CPF), IR/EM analysis, and physical verification (LVS, DRC, antenna, ERC). - Partner with RTL, DFT, analog/mixed-signal, package, and CAD teams to define floorplan, clocking, and power delivery strategies while establishing methodology scripts and flows.
What you'll need
- Bachelor's degree in Electrical Engineering, Computer Engineering, or related field. - 8+ years of physical design experience with multiple tapeouts on advanced process nodes (7nm or below). - Deep expertise in synthesis, place & route, CTS, and timing closure using industry-standard tools (Synopsys Fusion Compiler / ICC2, Cadence Innovus, PrimeTime). - Strong command of low-power design techniques (multi-Vt, power gating, DVFS, UPF). - Proficiency in Tcl/Python scripting for flow automation. - Proven track record delivering high-frequency, high-complexity SoC blocks or full-chip implementations to production.
Nice to have
- MS in Electrical Engineering or Computer Engineering. - Experience with high-speed SerDes-heavy designs, PCIe Gen 6/7, or UALink/UCIe-based connectivity SoCs. - Hands-on experience with hierarchical implementation and full-chip integration of large designs (>500M gates). - Familiarity with EMIR, thermal, and package co-design considerations. - Experience mentoring senior engineers and driving methodology adoption across teams.
Skills: RTL to GDS, Synthesis, PnR, STA, DRC/LVS
This role has been open 208 days — well above the 66-day median for Physical Design roles.
Physical Design · Physical Design
|
Open roles in category
676
|
Median days open
66 d
|
Median salary
$186k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Astera Labs | All employers we track in this specialty (676 roles · 79 employers) |
|---|---|---|
| Open roles in this specialty | 19 | 676 |
| Open roles in the wider Physical Implementation family | 24 | 1491 · 109 employers |
| Median days open | 95 d | 66 d (+29 d vs this employer) |
| Median salary (USD postings) | — | $186k |
Skills observed across this category: RTL to GDS, Synthesis, PnR, STA, DRC/LVS
Who's hiring in this category
- Qualcomm · 123 open roles · median 49 d
- AMD · 63 open roles · median 28 d
- Intel Corporation · 40 open roles · median 18 d
- Synopsys · 37 open roles · median 40 d
- NVIDIA · 36 open roles · median 68 d
- Broadcom · 35 open roles · median 105 d
How we counted: 676 open Physical Design (Physical Design) roles from 79 employers tracked in the SemiconductorJobs index, counted 26 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Physical Implementation family row. Figures refresh nightly.