Principal Physical Design Engineer - Irvine, CA, United States
$150,000 - $250,000 USD yearly
Originally posted 12 June 2026 by the employer.
About the role
Celero is seeking a Principal Physical Design Engineer to drive physical implementation flow from RTL to GDSII, covering floorplanning, place-and-route, clock tree synthesis, timing closure, and physical verification. The role focuses on tapeout execution across advanced technology nodes including 7nm, 5nm, and 3nm.
What you'll do
- Own RTL-to-GDSII physical implementation of SoCs or complex digital blocks. - Manage floorplanning, bump planning, power grid design, and clock tree synthesis (CTS) to optimize performance, power, and area (PPA). - Resolve timing closure, congestion, and EM/IR issues in collaboration with frontend design teams. - Run Static Timing Analysis (STA) and physical verification, resolving Design Rule Checking (DRC) and Layout Versus Schematic (LVS) violations. - Drive automation and improve flow robustness using scripting languages including Tcl, Python, or Perl. - Partner with architecture, logic design, and analog design teams to achieve tapeout readiness.
What you'll need
- 5+ years of relevant ASIC physical design experience. - Deep tapeout experience in advanced technology nodes (such as 7nm, 5nm, or 3nm). - Advanced proficiency with industry-standard EDA tools such as Innovus, Tempus, Voltus, Pegasus, or Calibre. - Demonstrated expertise in physically aware synthesis, power domain analysis, and Electromigration/IR-drop (EM/IR) cleanup. - Hands-on scripting capability in Tcl, Python, or Perl.
Skills: Physical Verification, TSMC nodes, DRC/ERC/LUP/PERC, ICV/Calibre, Floorplanning
This role has been open 133 days — well above the 63-day median for Physical Design roles.
Physical Design · Physical Design
|
Open roles in category
673
|
Median days open
63 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Celero | All employers we track in this specialty (673 roles · 79 employers) |
|---|---|---|
| Open roles in this specialty | 8 | 673 |
| Open roles in the wider Physical Implementation family | 8 | 1494 · 109 employers |
| Median days open | 49 d | 63 d (−14 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: Physical Verification, TSMC nodes, DRC/ERC/LUP/PERC, ICV/Calibre, Floorplanning
Who's hiring in this category
- Qualcomm · 122 open roles · median 46 d
- AMD · 63 open roles · median 27 d
- Intel Corporation · 40 open roles · median 15 d
- NVIDIA · 38 open roles · median 68 d
- Synopsys · 37 open roles · median 37 d
- Broadcom · 34 open roles · median 102 d
How we counted: 673 open Physical Design (Physical Design) roles from 79 employers tracked in the SemiconductorJobs index, counted 23 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Physical Implementation family row. Figures refresh nightly.