Principal Physical Design Engineer
$143,800 - $230,000 USD yearly
Originally posted 31 October 2026 by the employer.
About the role
Broadcom’s ASIC Products Division (APD) is looking for a Principal Physical Design Engineer to lead physical design implementation tasks for high-performance networking, AI/ML accelerators, and custom cloud ASICs. You will drive block-level floorplanning, synthesis, Place and Route (P&R), clock tree synthesis (CTS), timing closure, and signoff across deep sub-micron nodes including N5, N3, N2, and A14.
What you'll do
- Lead block-level and top-level physical implementation from floorplanning to GDSII stream-out using Cadence Innovus.
- Drive floorplanning, placement, CTS, routing, and timing and power optimization on advanced technology nodes (5nm, 3nm, 2nm) using multi-patterning and complex metal stacks.
- Perform multi-corner multi-mode (MCMM) static timing analysis (STA) and signal integrity (SI) optimization.
- Conduct power grid optimization, including static and dynamic IR-drop and electromigration (EM) signoff using PrimeTime, Voltus, or RedHawk.
What you'll need
- B.S. or M.S. degree in Electrical Engineering, Computer Engineering, or a related technical field.
- 12+ years of hands-on physical design experience successfully taping out high-frequency, ultra-large-scale networking or AI ASICs.
- Direct experience executing tapeouts in TSMC advanced nodes (N7, N5, N3) or equivalent foundry processes.
- High proficiency in major physical design tool flows: Cadence Innovus for P&R, Synopsys PrimeTime or Cadence Tempus for STA, StarRC / QRC and RedHawk for extraction and IR/EM, and Siemens Calibre for DRC/LVS.
- Advanced TCL, Python, and Unix shell scripting for flow automation and database manipulation.
Nice to have
- Strong background in high-speed clock network implementation, including H-tree, mesh, and low-power CTS.
- Experience with power-aware implementation flows, including UPF/CPF, multi-voltage domains, and clock/power gating.
Skills: Innovus, P&R, floorplanning, CTS, STA, signoff
More semiconductor jobs: Broadcom jobs · Physical design jobs
This role has been open 0 days — well below the 59-day median for Physical Design roles.
Physical Design · Physical Design
|
Open roles in category
693
|
Median days open
59 d
|
Category median salary (all employers)
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Broadcom | All employers we track in this specialty (693 roles · 84 employers) |
|---|---|---|
| Open roles in this specialty | 45 | 693 |
| Open roles in the wider Physical Implementation family | 52 | 1537 · 112 employers |
| Median days open | 67 d | 59 d (+8 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: Innovus, P&R, floorplanning, CTS, STA, signoff
Who's hiring in this category
- Qualcomm · 111 open roles · median 52 d
- AMD · 63 open roles · median 33 d
- Synopsys · 40 open roles · median 45 d
- Broadcom (this employer) · 38 open roles · median 100 d
- NVIDIA · 37 open roles · median 70 d
- Intel Corporation · 36 open roles · median 22 d
How we counted: 693 open Physical Design (Physical Design) roles from 84 employers tracked in the SemiconductorJobs index, counted 31 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Physical Implementation family row. Figures refresh nightly.