Principal Photonics Package Architect - San Jose, California, United States
$185,000 - $240,000 USD yearly
Originally posted 31 July 2026 by the employer — open 41 days.
About the role
It focuses on aligning electrical, thermal, and mechanical design requirements across functions, enabling robust package implementation, and guiding package technology decisions for NPO and CPO products.
What you'll do
- Define photonics package architecture, electrical and optical interface specifications, and establish signal integrity and power integrity requirements.
- Establish and manage Thermal Design Power (TDP) budgets and thermal performance targets.
- Drive cross-functional alignment with EIC, PIC, and hardware teams on co-design constraints and drive system optical link budget.
- Partner with validation, test, and reliability teams to define DFT and DFR requirements and acceptance criteria.
- Finalize bump map and ball map, and manage ECOs and revision control of package design databases.
- Lead package-level design reviews and own the package design technical roadmap.
What you'll need
- B.S., M.S., or Ph.D. in Electrical Engineering, Mechanical Engineering, Materials Science, Physics, or a related field.
- 10+ years of experience in semiconductor or photonics package development, package design, or package integration, with demonstrated technical leadership.
- Strong understanding of package architecture tradeoffs across electrical, optical, thermal, mechanical, and manufacturability considerations.
- Experience working across chip, board, and system-level design electrical and optical interfaces in complex product development environments.
- Experience with package EDA tools and electrical simulation tools, including Cadence APD+ and Ansys HFSS.
- Experience with advanced packaging design, including 2.5D and 3D package architectures.
- Familiarity with package design flows, design database management, and engineering change control practices.
- Ability to drive technical decisions, resolve cross-functional issues, and communicate architecture direction clearly to stakeholders.
- Strong foundation in design reviews, risk assessment, and design quality from concept through production release.
Nice to have
- Familiarity with design for test, reliability, and manufacturing.
This role has been open 37 days — well below the 59-day median for Packaging Engineering roles.
Packaging Engineering · Advanced Packaging
|
Open roles in category
289
|
Median days open
59 d
|
Median salary
$180k
|
See the full market breakdown ▾Category comparison, and who else is hiring
| Metric | Astera Labs | All employers we track in this specialty (289 roles · 54 employers) |
|---|---|---|
| Open roles in this specialty | 3 | 289 |
| Open roles in the wider Process, Fab & Equipment family | 10 | 9211 · 109 employers |
| Median days open | 37 d | 59 d (−22 d vs this employer) |
| Median salary (USD postings) | — | $180k |
Who's hiring in this category
- KLA Corporation · 49 open roles · median 96 d
- Micron Technology · 26 open roles · median 35 d
- Infineon Technologies · 25 open roles · median 34 d
- Renesas Electronics · 21 open roles · median 15 d
- Intel Corporation · 16 open roles · median 50 d
- Lumilens · 12 open roles · median 34 d
How we counted: 289 open Packaging Engineering (Advanced Packaging) roles from 54 employers tracked in the SemiconductorJobs index, counted 10 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Process, Fab & Equipment family row. Figures refresh nightly.