Principal PCS/PMA RTL Design Engineer

Design PCS and PMA digital logic for Ethernet, PCIe, UCIe, and UALink high-speed interconnect standards.

Originally posted 3 November 2026 by the employer.

About the role

Astera Labs is seeking a Principal PCS/PMA RTL Design Engineer to join the San Jose design team, focused on Physical Coding Sublayer (PCS) and Physical Medium Attachment (PMA) logic for high-speed interconnect standards such as Ethernet, PCIe, UCIe, and UALink. You will contribute to the architecture, implementation, integration, and verification of PCS/PMA digital logic for high-performance connectivity and networking ASICs.

What you'll do

• Develop synthesizable Verilog/SystemVerilog RTL for PCS and PMA digital blocks supporting Ethernet, PCIe, UCIe, UALink, and related protocols.
• Implement PCS functions including line encoding/decoding (64b/66b, 128b/130b, 8b/10b), scrambling/descrambling, block and word alignment, lane deskew and reordering, gearboxes, elastic buffers/FIFOs, rate adaptation, and forward error correction (RS-FEC/KP4).
• Implement PMA digital interface logic such as SerDes datapath interfaces (PIPE, SerDes-facing parallel interfaces, UCIe PHY/raw-die interfaces), clock and data recovery (CDR) control, equalization, and link-training control.
• Design lane-level and multi-lane logic, including lane bonding, polarity and lane reversal, PRBS generation/checking, loopback modes, and BIST features.
• Collaborate with design verification teams to define functional requirements, test plans, and coverage goals, and support lint, clock-domain crossing (CDC), and reset-domain crossing (RDC) checks.
• Support logic synthesis, constraints development, Static Timing Analysis (STA), timing closure, DFT integration, and silicon bring-up through tapeout.

What you'll need

• Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field.
• 3+ years of relevant experience in digital ASIC, SoC, or RTL design, or equivalent academic and industry experience.
• Hands-on experience with Verilog or SystemVerilog RTL development.
• Understanding of digital design fundamentals, including combinational and sequential logic, clocks, resets, state machines, datapaths, FIFOs, and interfaces.
• Working knowledge of at least one high-speed serial protocol (Ethernet, PCIe, UCIe, UALink, CXL, or similar) at the PCS/PHY layer.
• Experience with RTL simulation, debugging, synthesis, and basic timing analysis.
• Ability and willingness to work onsite in San Jose, California.

Nice to have

• Master's degree in Electrical Engineering, Computer Engineering, or a related field.
• Direct experience designing PCS, PMA, or PHY digital logic for Ethernet (25G–224G per lane, 100G/200G/400G/800G/1.6T), PCIe (Gen4/5/6/7), UCIe, UALink, CXL, or similar standards.
• Experience with PAM4 signaling, FEC (RS-FEC/KP4, FLIT-mode FEC/CRC), lane deskew/alignment, link training, and equalization control.
• Familiarity with the PIPE specification, 802.3 Clause 73/72/136/162-series, PCIe LTSSM, and UCIe link training and sideband.
• Familiarity with synthesis and implementation tools such as Cadence Genus/Innovus or Synopsys Design Compiler/ICC2, and STA tools such as Synopsys PrimeTime or Cadence Tempus.
• Experience with UVM, SystemVerilog Assertions, functional coverage, or verification-plan development.
• Exposure to advanced-node CMOS design (e.g., 5nm/3nm), tapeout, silicon bring-up, or post-silicon validation.

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