Principal PCIe Subsystem RTL lead

About the role

What you'll do

• Own the PCIe subsystem microarchitecture, defining internal block boundaries, data paths, and control interfaces.
• Lead the integration of third-party PCIe controller and PHY hard IP, including wrapper RTL.
• Define and implement bifurcation and lane-configuration logic for various lane-width configurations.
• Specify and drive implementation of the Transaction Layer pipeline, including TLP reception, classification, and routing.
• Define the Virtual Channel and flow-control architecture, ensuring fair arbitration and back-pressure handling.
• Lead PCIe silicon bring-up planning, including sequence definition, debug instrumentation, and loopback modes.

What you'll need

• 10+ years of digital IC design experience, with at least 4 years focused on PCIe subsystem design or integration.
• Deep expertise in PCIe architecture: Transaction Layer, Data Link Layer, Physical Layer, TLP structure, flow control, Virtual Channels, and error handling.
• Hands-on experience integrating PCIe hard IP (controller and/or SerDes PHY) into production SoC or chiplet designs, including wrapper RTL, reset sequencing, and PnR constraints.
• Strong SystemVerilog RTL skills for complex pipelined state machines, FIFOs, arbiters, and control logic.
• CXL 1.1/2.0 or 3.0 protocol knowledge, particularly CXL.io and CXL.mem transaction handling.
• Competency in multi-clock-domain design: async FIFO, CDC synchronizers, and clock crossing.

Nice to have

• Experience with UCIe or another die-to-die protocol at the PCIe TLP adaptation layer.
• Prior experience with protocol bridging or gearbox designs that span multiple PCIe generations.
• Familiarity with PCIe IP integration, including customization and support engagement.
• Experience at an advanced-node (7 nm or below) tape-out, particularly with timing closure and floorplan considerations for designs.

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