Principal Package Design Engineer - Austin, United States

Originally posted 26 September 2026 by the employer.

About the role

As a Principal Package Design Engineer, you will lead the development and integration of packaging solutions for high-performance semiconductors and electronic products.

What you'll do

• Lead the design, development, and qualification of advanced semiconductor packaging solutions, including Flip-chip, Chip Embedding, Wafer-level packaging (WLP/FOWLP), Panel-level packaging, 2.5D/3D packaging, System-in-package (SiP), Ball grid array (BGA/CSP), and Wafer-to-wafer and die-to-wafer heterogeneous bonding.
• Define package architecture based on electrical, thermal, mechanical, reliability, and cost requirements with hands-on simulation expertise.
• Drive package technology and OSAT selection and development for new product introductions (NPI).
• Oversee package layout reviews, stack-up definition, material selection, and interconnect strategy.
• Perform and guide others on simulations and analysis related to signal integrity/power integrity, thermal performance, mechanical stress/warpage, and design for manufacturability (DFM).
• Develop assembly flows and process requirements for OSATs and manufacturing partners, and lead package qualification activities including DOE planning, failure analysis, and reliability testing.
• Resolve packaging-related issues and challenges during NPI prototype builds, qualification, and production ramp.
• Create and maintain package specifications, design rules, process documentation, and technical reports.

What you'll need

• MSc or PhD degree in Electrical Engineering, Materials Science, Mechanical Engineering, Chemical Engineering, or a related field.
• 5+ years of experience in advanced semiconductor packaging or advanced electronics packaging and system integration.
• Strong hands-on knowledge of advanced packaging technologies, materials, assembly processes, and application system integration as they apply to AI infrastructure and data center power management.
• Deep understanding of thermal, mechanical, and electrical interactions in package design.
• Extensive, hands-on model setup, simulations, and analysis, and strong background in CAD and simulation tools.
• Experience with package reliability testing and qualification standards.
• Experience working with OSATs, substrate vendors, assembly houses, and semiconductor supply chains.
• Proven ability to troubleshoot packaging failures and drive root cause/corrective action.

Nice to have

• Experience with power semiconductor devices and packaging including Si/SiC/GaN MOSFETs, Power Modules, Intelligent Power Modules.
• Experience with power products in high-performance computing, AI/ML hardware, or mobile products.
• Hands-on experience with tools for package design and simulation such as Cadence Allegro Package Designer, SolidWorks, ANSYS, COMSOL, JMP / Minitab.
• Knowledge of JEDEC standards, IPC standards, and semiconductor qualification methods.
• Experience in W2W, D2W, D2D 3D heterogeneous integration and chiplet-based packaging.