Packaging SIPI Engineer, Sr. Staff

Originally posted 16 October 2026 by the employer.

This role focuses on optimizing package design and system simulation for IPs such as LPDDR, PCIe, UFS, and USB.

About the role

This role involves optimizing overall package design and performing system simulations for signal integrity and power integrity, specifically for auto products. The work includes defining system level constraints for IPs like LPDDR, PCIe, UFS, and USB.

What you'll do

• Perform package extraction for time domain and frequency domain analysis.
• Conduct system-level analysis for DDR, SerDes, and Mixed signal interfaces.
• Provide design guidelines for Package design.
• Perform system simulation and provide feedback for design optimization.
• Develop design and analysis flows and automate processes.
• Create technical documentation and presentations.

What you'll need

• Bachelor's degree in Chemical Engineering, Electrical Engineering, Mechanical Engineering, or related field and 6+ years of System/Package Design/Technology Engineering experience; OR Master's degree in Chemical Engineering, Electrical Engineering, Mechanical Engineering, or related field and 5+ years of experience; OR PhD in Chemical Engineering, Electrical Engineering, Mechanical Engineering, or related field and 4+ years of experience.
• Experience working across multiple organizations including PHY, Package, and PCB teams.
• Ability to work independently and provide technical guidance for key decision-making processes.

Nice to have

• Experience in AUTO package design and analysis.
• Experience in SerDes design specifications such as PCIe Gen-x, USB, UFS in Server design.
• Experience in Matlab for automating existing simulation flow.
• Experience in programming language (c/c++) or scripting language (Perl/Python).
• Experience in Electromagnetics and solid background on transmission line theory and Crosstalk.
• Proficiency in field solvers such as HFSS, Q3D, Sentinel-PSI, and Clarity.
• Experience in simulation tools such as ADS and Hspice.
• Working knowledge in Cadence Allegro/APD/Sip or Mentor Xpedition.
• Prior Management experience.
• 10 years of experience in DDR/SerDes in Package/PCB/System Design related to Compute/Server standards.

Skills: package extraction, time domain analysis, frequency domain analysis, DDR, SerDes, Mixed signal interfaces, Package design guidelines