Principal IP Verification Engineer - Chandler, Arizona, United States
$249,900 - $338,100 USD yearly
Originally posted 15 September 2026 by the employer.
About the role
The Principal IP Verification Engineer is a lead-by-doing role within the Solution Engineering division, leading a team of verification engineers and developing testbenches and test suites.
What you'll do
- Establish and maintain verification architecture, ensuring the design verification team's work aligns to this strategy. - Write and review test plans, define test methodologies, and complete functional verification to required quality levels and schedules. - Collaborate with architecture, design, and verification teams to build a functional verification strategy and deliver quality for each product release. - Develop IP features which enable reconfigurable designs. - Partner with design teams to review microarchitectural specifications and debug issues.
What you'll need
- Bachelor's degree or higher in Computer Science, Electrical/Computer Engineering, or a related field. - Experience in functional verification of complex subsystems or SoCs across requirements collection, test plan creation, testbench implementation, test case development, documentation, and support. - Experience with front-end verification tools, including dynamic simulation tools, static simulation tools, UPF, debuggers, Questa, VCS, Jasper Gold, and Verdi. - Experience measuring and closing functional coverage, toggle coverage, and code coverage. - Experience with reconfigurable IP or subsystem design.
Nice to have
- Object-oriented programming concepts. - Experience with ARM-based designs or ARM System Architectures. - Experience with OTP/Fuse usage models and JTAG/TAP protocols. - Scripting experience in Perl, Python, or other scripting languages. - SoC system debug methodologies. - DFT methodologies, including RTL testability, scan insertion, and OCC.
Skills: functional verification, testbench, VCS, Questa, coverage
This role has been open 0 days — well below the 64-day median for Design Verification roles.
Design Verification · Design Verification
|
Open roles in category
1277
|
Median days open
64 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Arm Holdings | All employers we track in this specialty (1277 roles · 96 employers) |
|---|---|---|
| Open roles in this specialty | 49 | 1277 |
| Open roles in the wider Digital Design & Verification family | 118 | 3384 · 117 employers |
| Median days open | 78 d | 64 d (+14 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: functional verification, testbench, VCS, Questa, coverage
Who's hiring in this category
- Qualcomm · 112 open roles · median 42 d
- AMD · 92 open roles · median 57 d
- NVIDIA · 91 open roles · median 67 d
- Synopsys · 73 open roles · median 42 d
- SiFive · 56 open roles · median 81 d
- Apple · 55 open roles · median 8 d
How we counted: 1277 open Design Verification (Design Verification) roles from 96 employers tracked in the SemiconductorJobs index, counted 28 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.