Principal IP Signoff & Methodology Engineer - San Jose, California, United States
$175,000 - $230,000 USD yearly
Originally posted 29 April 2026 by the employer.
About the role
Astera Labs is looking for a Principal IP Signoff & Methodology Engineer to own the readiness, quality, and signoff of internal and external IP blocks before release into SoC and system implementation flows. This role drives signoff closure and revision management across RTL, SDC, LEF/DEF, netlists, timing, physical verification, and package-aware considerations.
What you'll do
- Own the completeness, consistency, configuration management, and signoff readiness of internal and external IP deliverables across supported usage profiles. - Review and validate key deliverables including RTL, timing constraints (SDC), synthesized netlists, LEF/DEF, and floorplan collateral. - Define and maintain IP signoff checklists, release criteria, quality gates, and acceptance requirements for reusable IP. - Run, review, and debug physical verification signoff checks such as DRC, LVS, PERC, and package-aware assembly views. - Triage digital, physical, analog, and mixed-signal signoff issues, identifying root causes to drive closure with design, layout, and CAD teams.
What you'll need
- Experience driving digital and physical design signoff for IP blocks and SoC integration. - Expertise in signoff verification flows including static timing analysis, DRC, LVS, and PERC. - Hands-on proficiency with RTL, timing constraints (SDC), synthesized netlists, and LEF/DEF handoff views. - Deep understanding of IP release criteria, quality gates, and configuration management for reusable collateral. - Strong debug ownership across digital, physical, analog, and mixed-signal IP interfaces.
Skills: IP Lifecycle Management, Calibre, PrimeTime, Verilog, FinFET
This role has been open 178 days — well above the 71-day median for EDA/CAD Engineering roles.
EDA/CAD Engineering · EDA Tools
|
Open roles in category
696
|
Median days open
71 d
|
Median salary
$192k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Astera Labs | All employers we track in this specialty (696 roles · 75 employers) |
|---|---|---|
| Open roles in this specialty | 5 | 696 |
| Open roles in the wider Physical Implementation family | 24 | 1489 · 109 employers |
| Median days open | 58 d | 71 d (−13 d vs this employer) |
| Median salary (USD postings) | — | $192k |
Skills observed across this category: IP Lifecycle Management, Calibre, PrimeTime, Verilog, FinFET
Who's hiring in this category
- Cadence Design Systems · 155 open roles · median 152 d
- Synopsys · 62 open roles · median 43 d
- Micron Technology · 44 open roles · median 52 d
- GlobalFoundries · 39 open roles · median 26 d
- Qualcomm · 39 open roles · median 76 d
- Keysight Technologies · 34 open roles · median 79 d
How we counted: 696 open EDA/CAD Engineering (EDA Tools) roles from 75 employers tracked in the SemiconductorJobs index, counted 25 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Physical Implementation family row. Figures refresh nightly.