Principal High-Speed Analog Layout Design Engineer - Ottawa, Ontario, Canada
Originally posted 18 August 2026 by the employer — open 34 days. Relisted by the employer on 22 September 2026.
About the role
This role involves driving the layout design of complex analog and mixed-signal IP blocks, specifically ADCs, DACs, and PLLs, critical for advanced optical communication systems.
What you'll do
- Lead the physical layout design of complex analog/mixed-signal macros, from floor planning through final verification.
- Collaborate with schematic designers to create optimal layout solutions considering performance, matching, symmetry, and reliability.
- Mentor and guide junior layout engineers/contractors, enforcing best practices in layout design and verification.
- Perform and debug full hierarchy LVS, DRC, PERC, ERC, and other signoff checks using industry-standard tools (Pegasus, Calibre).
- Contribute to chip-level planning including top-level floor planning, block integration, power grid implementation, and signal routing.
- Support automation initiatives through scripting and tool customization.
What you'll need
- Minimum 10+ years of hands-on analog/mixed-signal layout design experience in advanced CMOS/FinFET technologies.
- Proven track record of top-level integration IP layout macros and preparing IPs for handoff to Physical Design.
- Proven leadership in owning major IP layout macros or full-chip-level layout at FinFET nodes.
- At least 1 year of experience with TSMC FinFET process nodes (N3, N5, N7, or N16).
- Deep understanding of device physics, layout-dependent effects (LOD, WPE, OSE, LDE), and their impact on circuit performance.
- Strong expertise in layout best practices for device matching, noise isolation, ESD protection, symmetry, and parasitic minimization.
- Proficiency in floor planning, hierarchical block integration, routing strategy, and power/ground grid design.
- Expertise with Cadence Virtuoso, Calibre, Pegasus, and other layout and verification tools.
- Familiarity with layout verification flows, including LVS, DRC, PERC, Density, DFM, ERC, and Antenna rules.
- Experience using revision control systems for layout design management.
Nice to have
- Exposure to optical or high-speed analog interfaces.
- Working knowledge of SKILL, TCL, or Python for layout automation or design flow optimization.
Skills: analog layout, FinFET, Cadence Virtuoso, DRC LVS, floor planning
This role has been open 34 days — well above the 18-day median for Analog IC Design roles.
Analog IC Design · Analog Layout
|
Open roles in category
38
|
Median days open
18 d
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Median salary
—
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See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Celero | All employers we track in this specialty (38 roles · 22 employers) |
|---|---|---|
| Open roles in this specialty | 8 | 38 |
| Open roles in the wider Analog & Mixed-Signal family | 13 | 1331 · 105 employers |
| Median days open | 24 d | 18 d (+6 d vs this employer) |
| Median salary (USD postings) | — | — |
Skills observed across this category: analog layout, FinFET, Cadence Virtuoso, DRC LVS, floor planning
Who's hiring in this category
- Analog Devices · 4 open roles · median 6 d
- Celero (this employer) · 4 open roles · median 13 d
- Marvell Technology · 3 open roles · median 17 d
- QORVO · 3 open roles · median 25 d
- Renesas Electronics · 3 open roles · median 6 d
- Infineon Technologies · 2 open roles · median 34 d
How we counted: 38 open Analog IC Design (Analog Layout) roles from 22 employers tracked in the SemiconductorJobs index, counted 22 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Analog & Mixed-Signal family row. Figures refresh nightly.