Principal High-Speed Analog Layout Design Engineer - Irvine, CA, United States
$150,000 - $250,000 USD yearly
Originally posted 9 September 2026 by the employer — open 1 day.
About the role
This role involves driving the physical layout design of complex analog and mixed-signal IP blocks for advanced optical communication systems.
What you'll do
- Lead the physical layout design of complex analog/mixed-signal macros (e.g., ADCs, DACs, PLLs) from floor planning through final verification.
- Collaborate with schematic designers to create optimal layout solutions considering performance, matching, symmetry, and reliability.
- Mentor and guide junior layout engineers/contractors, enforcing best practices in layout design and verification.
- Perform and debug full hierarchy LVS, DRC, PERC, ERC, and other signoff checks using industry-standard tools (Pegasus, Calibre).
- Contribute to chip-level planning including top-level floor planning, block integration, power grid implementation, and signal routing.
- Participate in layout design reviews and provide technical leadership for layout quality, verification completeness, and schedule adherence.
What you'll need
- 10+ years of hands-on analog/mixed-signal layout design experience in advanced CMOS/FinFET technologies.
- Experience with top-level integration IP layout macros and preparing IPs for handoff to Physical Design.
- Leadership in owning major IP layout macros or full-chip-level layout at FinFET nodes.
- At least 1 year of experience with TSMC FinFET process nodes (N3, N5, N7, or N16).
- Deep understanding of device physics, layout-dependent effects (LOD, WPE, OSE, LDE), and their impact on circuit performance.
- Expertise with Cadence Virtuoso, Calibre, Pegasus, and other layout and verification tools.
Nice to have
- Exposure to optical or high-speed analog interfaces.
- Working knowledge of SKILL, TCL, or Python for layout automation or design flow optimization.
- Ability to collaborate with international teams (U.S., Canada, Argentina).
Skills: physical layout design, ADCs, DACs, PLLs, Cadence Virtuoso, FinFET technologies
This role has been open 1 day — well below the 14-day median for Analog IC Design roles.
Analog IC Design · Analog Layout
|
Open roles in category
30
|
Median days open
14 d
|
Median salary
—
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Celero | All employers we track in this specialty (30 roles · 19 employers) |
|---|---|---|
| Open roles in this specialty | 4 | 30 |
| Open roles in the wider Analog & Mixed-Signal family | 9 | 1317 · 100 employers |
| Median days open | 1 d | 14 d (−13 d vs this employer) |
| Median salary (USD postings) | — | — |
Skills observed across this category: physical layout design, ADCs, DACs, PLLs, Cadence Virtuoso, FinFET technologies
Who's hiring in this category
- Celero (this employer) · 4 open roles · median 1 d
- Infineon Technologies · 3 open roles · median 29 d
- QORVO · 3 open roles · median 13 d
- Marvell Technology · 2 open roles · median 5 d
- Monolithic Power Systems · 2 open roles · median 15 d
- onsemi · 2 open roles · median 15 d
How we counted: 30 open Analog IC Design (Analog Layout) roles from 19 employers tracked in the SemiconductorJobs index, counted 10 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Analog & Mixed-Signal family row. Figures refresh nightly.