Principal High-Speed Analog Layout Design Engineer - San Jose, CA, United States
$150,000 - $250,000 USD yearly
Originally posted 18 August 2026 by the employer. Relisted by the employer on 22 September 2026.
About the role
This role involves driving the layout design of complex analog and mixed-signal IP blocks for advanced optical communication systems. You will lead layout development for critical blocks such as ADCs, DACs, and PLLs.
What you'll do
- Lead physical layout design of complex analog/mixed-signal macros (e.g., ADCs, DACs, PLLs), from floor planning through final verification.
- Collaborate with schematic designers to create optimal layout solutions considering performance, matching, symmetry, and reliability.
- Mentor and guide junior layout engineers/contractors across multiple time zones, enforcing best practices in layout design and verification.
- Perform and debug full hierarchy LVS, DRC, PERC, ERC, and other signoff checks using industry-standard tools (Pegasus, Calibre, etc.).
- Contribute to chip-level planning including top-level floor planning, block integration, power grid implementation, and signal routing.
- Participate in layout design reviews and provide technical leadership for layout quality, verification completeness, and schedule adherence.
What you'll need
- Minimum 10+ years of hands-on analog/mixed-signal layout design experience in advanced CMOS/FinFET technologies.
- Proven leadership in owning major IP layout macros or full-chip-level layout at FinFET nodes.
- At least 1 year of experience with TSMC FinFET process nodes (N3, N5, N7, or N16).
- Deep understanding of device physics, layout-dependent effects (LOD, WPE, OSE, LDE), and their impact on circuit performance.
- Strong expertise in layout best practices for device matching, noise isolation, ESD protection, symmetry, and parasitic minimization.
- Proficiency in floor planning, hierarchical block integration, routing strategy, and power/ground grid design.
- Expertise with Cadence Virtuoso, Calibre, Pegasus, and other layout and verification tools.
- Familiarity with layout verification flows, including LVS, DRC, PERC, Density, DFM, ERC, and Antenna rules.
- Experience using revision control systems for layout design management.
Nice to have
- Exposure to optical or high-speed analog interfaces.
- Working knowledge of SKILL, TCL, or Python for layout automation or design flow optimization.
Skills: analog/mixed-signal macros, ADCs, DACs, PLLs, Cadence Virtuoso, Calibre
This role has been open 40 days — well above the 24-day median for Analog IC Design roles.
Analog IC Design · Analog Layout
|
Open roles in category
45
|
Median days open
24 d
|
Median salary
—
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Celero | All employers we track in this specialty (45 roles · 21 employers) |
|---|---|---|
| Open roles in this specialty | 8 | 45 |
| Open roles in the wider Analog & Mixed-Signal family | 13 | 1364 · 107 employers |
| Median days open | 30 d | 24 d (+6 d vs this employer) |
| Median salary (USD postings) | — | — |
Skills observed across this category: analog/mixed-signal macros, ADCs, DACs, PLLs, Cadence Virtuoso, Calibre
Who's hiring in this category
- Celero (this employer) · 8 open roles · median 30 d
- Analog Devices · 6 open roles · median 10 d
- Broadcom · 3 open roles · median 6 d
- Marvell Technology · 3 open roles · median 23 d
- onsemi · 3 open roles · median 33 d
- QORVO · 3 open roles · median 31 d
How we counted: 45 open Analog IC Design (Analog Layout) roles from 21 employers tracked in the SemiconductorJobs index, counted 28 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Analog & Mixed-Signal family row. Figures refresh nightly.