$164,800 USD yearly
Originally posted 22 August 2025 by the employer — open 383 days.
About the role
This role is accountable for system-level electrical design and for establishing signal and power integrity simulation methodologies that underpin the development of hardware platforms for MEMS timing products.
What you'll do
- Lead signal integrity (SI) design initiatives for system platforms supporting advanced SiTime timing products.
- Establish comprehensive methodologies for signal and power integrity across hardware platforms, including validation environments, probing stations, load boards, and production test systems.
- Identify, assess, and integrate new technologies, components, and techniques to enhance overall signal and power integrity performance.
- Deliver robust and cost-effective signal integrity solutions by conducting detailed analysis, simulations, experimental design, and verification.
- Collaborate with circuit design, packaging, board design, and product teams to define reliable system components at all levels.
- Ensure delivery of high-quality, first-pass-success hardware infrastructure through root cause analysis and resolution of signal and power integrity challenges.
What you'll need
- Master's degree in Electrical Engineering, Computer Engineering, or related field.
- Over 10 years of expertise in hardware system design, including comprehensive signal integrity analysis and optimization.
- Proficiency in PCB design tools such as Altium, Allegro, and APD for thorough PCB reviews.
- In-depth knowledge of server technologies, including signal and power integrity design and optimization methodologies, thermal management strategies, and mechanical considerations.
- Experience in high-speed interface design, including DDR, PCIe, USB, and similar protocols.
- Strong background in transmission line and electromagnetic field theory, with expertise in time and frequency domain analysis.
- Skill in extracting S-parameters or lumped models from packages and PCBs, converting them to Spice/behavioral circuit models, and evaluating performance through simulation.
- Experience with MIPI, I2C, SPI, and UART interfaces.
- Proficiency in impedance-controlled board design and manufacturing.
- Ability to conduct laboratory measurements using oscilloscope, phase noise analyzer, VNA, and TDR.
Nice to have
- Leadership role experience.
- Strong sense of self-motivation and commitment to achieving meaningful results.
- Ability and enthusiasm to contribute effectively within a collaborative team environment.
- Exceptional communication, interpersonal, critical thinking, and problem-solving abilities.
- Proven capability to perform effectively under pressure while meeting stringent deadlines.
- Willingness and ability to adopt a hands-on approach when necessary.
Skills: signal integrity, power integrity, hardware platforms, simulation, PCB design tools, server technologies
This role has been open 169 days — well above the 91-day median for High-Speed IO/SerDes Design roles.
High-Speed IO/SerDes Design · Serdes Highspeed
|
Open roles in category
217
|
Median days open
91 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | SiTime | All employers we track in this specialty (217 roles · 44 employers) |
|---|---|---|
| Open roles in category | 1 | 217 |
| Median days open | 169 d | 91 d (+78 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: signal integrity, power integrity, hardware platforms, simulation, PCB design tools, server technologies
Who's hiring in this category
- AMD · 24 open roles · median 61 d
- Cadence Design Systems · 19 open roles · median 153 d
- Qualcomm · 17 open roles · median 74 d
- Synopsys · 16 open roles · median 53 d
- Broadcom · 11 open roles · median 142 d
- NVIDIA · 10 open roles · median 95 d
How we counted: 217 open High-Speed IO/SerDes Design (Serdes Highspeed) roles from 44 employers tracked in the SemiconductorJobs index, counted 10 Sept 2026. Figures refresh nightly.