AMD's Network Technology Solutions Group (NTSG) is developing system control-path FPGAs for high-speed networking products in AI data centers.
About the role
AMD's Network Technology Solutions Group (NTSG) is seeking a Principal FPGA Design Engineer to provide technical leadership in the architecture, design, development, integration, and validation of complex board-level products utilizing FPGAs, embedded processors, and advanced system technologies. You will lead the design and verification RTL, review board schematics, and drive system bring-up for networking products used in AI data centers.
What you'll do
- Define FPGA microarchitecture and detailed design specifications in collaboration with engineering teams and ODM/JDM partners.
- Design and develop system control-path FPGAs for networking products.
- Develop, integrate, simulate, and verify Verilog/SystemVerilog RTL code, including custom testbench creation.
- Execute the full FPGA development flow, covering synthesis, place and route, timing closure, and in-system hardware debugging.
- Collaborate with hardware, software, and diagnostic engineering teams to lead domestic and overseas system bring-ups and debugging.
- Develop Python, Tcl, or shell scripts to streamline data processing and automate FPGA design workflows.
What you'll need
- Bachelor's or Master's degree in Electrical Engineering, Electronics Engineering, Computer Engineering, or a related field.
- Experience with Verilog and SystemVerilog RTL design and verification.
- Experience executing synthesis, place and route, timing closure, and in-system hardware debugging.
- Scripting experience using Python, Tcl, or shell to automate design workflows.
Nice to have
- 12+ years of experience in FPGA/SOC design, implementation, and verification.
- Experience leading multiple full life-cycle FPGA designs for datacenter networking products.
- Knowledge of control interfaces including PCIe, I2C, MDIO, QSPI, Ethernet, USB, LPTI, and AXI.
- Proficiency with AMD/Xilinx Vivado, Vitis, and Lattice toolchains.
- Expertise in FPGA timing closure, floorplanning, CDC analysis, pipelining, and area/performance optimization.
More semiconductor jobs: AMD jobs · FPGA engineer jobs · California jobs
This role has been open 0 days — well below the 65-day median for FPGA Design roles.
FPGA Design · RTL Design
|
Open roles in category
108
|
Median days open
65 d
|
Category median salary (all employers)
$163k
|
See the full market breakdown ▾Category comparison, and who else is hiring
| Metric | AMD | All employers we track in this specialty (108 roles · 25 employers) |
|---|---|---|
| Open roles in this specialty | 14 | 108 |
| Median days open | 51 d | 65 d (−14 d vs this employer) |
| Median salary (USD postings) | — | $163k |
Who's hiring in this category
- Altera · 36 open roles · median 61 d
- AMD (this employer) · 12 open roles · median 69 d
- Teradyne · 8 open roles · median 89 d
- Keysight Technologies · 7 open roles · median 13 d
- Qualcomm · 7 open roles · median 66 d
- Microchip Technology · 6 open roles · median 87 d
How we counted: 108 open FPGA Design (RTL Design) roles from 25 employers tracked in the SemiconductorJobs index, counted 6 Nov 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there. Figures refresh nightly.