$180,000 - $200,000 USD yearly
High-speed analog ICs, optical transceivers, and LPO/LRO/CPO architectures for 800G, 1.6T, and 3.2T interconnect.
Originally posted 3 September 2026 by the employer.
About the role
This role acts as a technical strategist driving design wins and customer co-development across hyperscaler data centers for high-speed analog ICs in optical and copper connectivity. Focus areas include 800G, 1.6T, and 3.2T interconnect architectures including LPO, LRO, and CPO.
What you'll do
- Drive design wins for high-speed drivers, TIAs, copper redrivers, and other products with engineering teams at key data center customers.
- Lead co-development initiatives and joint proof-of-concept projects for 1.6T and 3.2T+ technologies with Tier 1 hyperscalers.
- Guide customers on hardware design, PCB layout, signal integrity optimization, firmware integration, and system validation.
- Troubleshoot and debug complex technical issues while delivering pre-sales and post-sales technical support for strategic design-ins.
- Support customer qualification processes with equipment manufacturers, network operators, and cloud service providers.
- Author application notes, white papers, and design guides while aligning Semtech product roadmaps with customer technology evolution plans.
What you'll need
- Bachelor's degree in Electrical Engineering or a related technical field.
- 8+ years of FAE experience demonstrating technical capability and strategic customer engagement.
- Expertise in signal integrity, including high-speed principles, modulation schemes, channel modeling, and equalization for 800G, 1.6T, and 3.2T applications.
- Knowledge of optical transceiver architecture, design, validation, and manufacturing, along with familiarity with LPO, LRO, and CPO architectures.
- Experience in high-speed PCB design covering layout, impedance control, and signal integrity validation.
- Proficiency with high-speed test equipment, such as network analyzers, BER testers, and oscilloscopes.
- Understanding of IEEE 802.3 and OIF standards, as well as hyperscaler data center architectures and network topologies.
Nice to have
- Master's or Ph.D. degree in Electrical Engineering or a related technical field.
- Direct experience with high-speed laser/modulator drivers, TIAs, redrivers, and/or DSPs.
- Active participation in industry standards bodies (IEEE 802.3, OIF) driving 1.6T/3.2T specifications.
- Prior experience at hyperscaler operators, optical module vendors, or data center equipment manufacturers.
- Established relationships with Tier 1 hyperscaler engineering teams and Bay Area ecosystem partners.
More semiconductor jobs: Hardware design jobs
This role has been open 56 days — slightly above the 48-day median for Hardware Systems Engineering roles.
Hardware Systems Engineering · AI ML Hardware
|
Open roles in category
1058
|
Median days open
48 d
|
Category median salary (all employers)
$154k
|
See the full market breakdown ▾Category comparison, and who else is hiring
| Metric | Semtech | All employers we track in this specialty (1058 roles · 102 employers) |
|---|---|---|
| Open roles in this specialty | 4 | 1058 |
| Open roles in the wider Software, Firmware & Systems family | 9 | 6295 · 144 employers |
| Median days open | 85 d | 48 d (+37 d vs this employer) |
| Median salary (USD postings) | — | $154k |
Who's hiring in this category
- Intel Corporation · 79 open roles · median 41 d
- KLA Corporation · 63 open roles · median 55 d
- Teradyne · 59 open roles · median 41 d
- Applied Materials · 51 open roles · median 58 d
- NVIDIA · 48 open roles · median 64 d
- ASML · 45 open roles · median 26 d
How we counted: 1058 open Hardware Systems Engineering (AI ML Hardware) roles from 102 employers tracked in the SemiconductorJobs index, counted 29 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Software, Firmware & Systems family row. Figures refresh nightly.