Principal Engineer, Silicon Validation
$200,000 - $255,000 USD yearly
Lead silicon validation and first bring-up for electronic-photonic SoCs and optical chiplets.
About the role
You will lead the silicon validation of electronic-photonic optical chiplets, defining and driving validation strategy from initial silicon power-on through block and chip-level signoff. The position covers high-speed SerDes, photonic systems, and post-silicon validation.
What you'll do
- Define and implement comprehensive validation methodologies for electronic-photonic SoCs, covering initial bringup, functional validation, electrical characterization, and system-level testing.
- Lead first silicon power-on and bringup for new tape-outs, collaborating with firmware and design teams to establish operating conditions and validate core functionality.
- Execute post-silicon validation of SerDes interfaces, optical control loops, and mixed-signal blocks using lab equipment including BERT, DCA, oscilloscopes, OSA, and VNA.
- Establish validation targets, coverage objectives, and signoff criteria using industry standards such as IEEE, OIF, JEDEC, and Ethernet/Optical MSA specifications.
- Investigate and resolve silicon failure modes ranging from signal integrity issues to mixed-signal anomalies using systematic debug methodologies.
- Provide technical leadership to validation engineers and deliver comprehensive validation reports and signoff packages.
What you'll need
- Bachelor's degree in Electrical Engineering or related field with 10+ years of relevant industry experience, or Master's degree with 7+ years of experience.
- Demonstrated leadership in post-silicon validation for complex SoCs or multi-chip packages, including first silicon bringup and full signoff.
- Hands-on expertise with high-speed SerDes validation and characterization (NRZ and PAM-4) using equipment such as BERTs, oscilloscopes/DCAs, and network analyzers.
- Strong proficiency in Python for lab automation, data analysis, and test infrastructure development.
- Experience developing and owning validation test plans end-to-end.
- Deep understanding of communication protocols and standards such as Ethernet and PCIe.
Nice to have
- Familiarity with optical transceiver standards and co-packaged optics integration challenges.
- Knowledge of high-speed standards: Ethernet (200G/400G/800G), PCIe Gen5/6, and OIF CEI.
- Experience driving NPI and transition from lab validation to manufacturing test.
More semiconductor jobs: Test engineer jobs · San Jose jobs
This role has been open 11 days — well below the 39-day median for Silicon Test Engineering roles.
Silicon Test Engineering · DFT Test
|
Open roles in category
638
|
Median days open
39 d
|
Category median salary (all employers)
$176k
|
See the full market breakdown ▾Category comparison, and who else is hiring
| Metric | Ayar Labs | All employers we track in this specialty (638 roles · 86 employers) |
|---|---|---|
| Open roles in this specialty | 9 | 638 |
| Open roles in the wider Silicon Validation & Test family | 13 | 2395 · 121 employers |
| Median days open | 25 d | 39 d (−14 d vs this employer) |
| Median salary (USD postings) | — | $176k |
Who's hiring in this category
- Teradyne · 83 open roles · median 37 d
- Infineon Technologies · 51 open roles · median 34 d
- Renesas Electronics · 45 open roles · median 33 d
- Texas Instruments · 33 open roles · median 44 d
- Qualcomm · 29 open roles · median 51 d
- Micron Technology · 25 open roles · median 55 d
How we counted: 638 open Silicon Test Engineering (DFT Test) roles from 86 employers tracked in the SemiconductorJobs index, counted 8 Nov 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Silicon Validation & Test family row. Figures refresh nightly.