Principal Engineer, SerDes Validation
$180,000 - $230,000 USD yearly
About the role
The Principal Engineer, SerDes Validation leads validation efforts to ensure optical chiplets and optical SerDes devices meet component and system-level requirements. The role focuses on high-speed characterization of electro-optic systems, multi-wavelength sources, and CMOS chiplets.
What you'll do
- Define and implement validation methodologies, test plans, and success criteria for optical chiplets at component and system levels.
- Collaborate with Design Engineering to bring up silicon photonic and laser products, troubleshooting and resolving issues on optical SerDes devices.
- Perform high-speed characterization of electro-optic systems using signal integrity (SI) and eye analysis techniques.
- Collaborate with multidisciplinary teams across bench characterization to drive New Product Introduction (NPI) from development to mass production.
- Author and maintain customer-facing validation reports and technical documentation covering product performance and reliability.
- Create and maintain software scripts and test hardware stations for validation test automation.
What you'll need
- Master's degree in Electrical Engineering or equivalent.
- 10+ years of experience with component and system test equipment (BERT, DCA, OSA, etc.) and standard signal quality metrics (TDECQ, SRS, URS).
- 5+ years of experience in programming languages (Python, etc.) for test automation and data analysis.
- Understanding of communication protocols and standards such as Ethernet and PCIe.
- Experience with SoC validation planning, bring-up, debugging, and optimization.
- Experience with high-speed SerDes characterization and optimization.
- Knowledge of data analysis, process control, and statistical methods.
Nice to have
- Ph.D. in Electrical Engineering, Computer Science, Computer Engineering, or a related field.
- 5+ years of hands-on experience in semiconductor laser & photonic device validation.
- Working knowledge of optical transceiver packaging and integration challenges.
- Project management skills.
More semiconductor jobs: Test engineer jobs · San Jose jobs
This role has been open 45 days — slightly above the 39-day median for Silicon Test Engineering roles.
Silicon Test Engineering · DFT Test
|
Open roles in category
638
|
Median days open
39 d
|
Category median salary (all employers)
$176k
|
See the full market breakdown ▾Category comparison, and who else is hiring
| Metric | Ayar Labs | All employers we track in this specialty (638 roles · 86 employers) |
|---|---|---|
| Open roles in this specialty | 9 | 638 |
| Open roles in the wider Silicon Validation & Test family | 13 | 2395 · 121 employers |
| Median days open | 25 d | 39 d (−14 d vs this employer) |
| Median salary (USD postings) | — | $176k |
Who's hiring in this category
- Teradyne · 83 open roles · median 37 d
- Infineon Technologies · 51 open roles · median 34 d
- Renesas Electronics · 45 open roles · median 33 d
- Texas Instruments · 33 open roles · median 44 d
- Qualcomm · 29 open roles · median 51 d
- Micron Technology · 25 open roles · median 55 d
How we counted: 638 open Silicon Test Engineering (DFT Test) roles from 86 employers tracked in the SemiconductorJobs index, counted 8 Nov 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Silicon Validation & Test family row. Figures refresh nightly.