Principal Engineer, Serdes Analog Design - San Jose, California, United States
$189,000 USD yearly
Originally posted 21 January 2026 by the employer.
About the role
As a Principal Engineer, Serdes Analog Design in the Advanced Circuit and Systems (ACAS) group, you will define architecture and circuits for high-speed interconnect transceiver (Serdes) IPs, clock generation, and traditional analog circuits while supervising designers through silicon validation and debugging. The work covers high-performance and low-power Serdes designs including display interfaces, camera sensor interfaces, UCIe / die-to-die interconnects, and 224/448Gbps UA-link/Ethernet.
What you'll do
- Define architecture and circuits for high-speed interconnect transceiver (Serdes) projects. - Supervise designers through design completion, layout optimization, silicon validation, and debugging. - Translate component design specifications to schematics and build simulation test-benches to evaluate performance, functionality, power consumption, and reliability. - Design low-power and low-voltage analog and custom digital circuit components using advanced CMOS process technologies. - Supervise the layout of the complete project and optimize layout to improve power consumption and circuit performance.
What you'll need
- Bachelor's degree with 20+ years, Master's with 18+ years, or PhD with 15+ years of experience. - Minimum of 7+ years of Analog/Serdes SoC design experience. - Hands-on circuit design experience with analog circuits and mixed-signal circuits such as bandgap, LDO, and filters. - Experience with Serdes IP circuits, including CTLE, DFE, FFE, clock distributions, PI, and IQ generation. - Knowledge of Serdes architecture and high-speed interconnect standards such as USB, PCIe, and UCIe. - Proficiency with EDA tools including Cadence, Spectre, Totem, and EMX. - Experience with scripting languages including Python and Matlab.
Skills: SerDes, high-speed interconnect, transceiver, analog design, circuit architecture
This role has been open 211 days — well above the 73-day median for High-Speed IO/SerDes Design roles.
High-Speed IO/SerDes Design · Serdes Highspeed
|
Open roles in category
244
|
Median days open
73 d
|
Median salary
$191k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Samsung Semiconductor | All employers we track in this specialty (244 roles · 47 employers) |
|---|---|---|
| Open roles in this specialty | 5 | 244 |
| Open roles in the wider Analog & Mixed-Signal family | 8 | 1439 · 106 employers |
| Median days open | 65 d | 73 d (−8 d vs this employer) |
| Median salary (USD postings) | — | $191k |
Skills observed across this category: SerDes, high-speed interconnect, transceiver, analog design, circuit architecture
Who's hiring in this category
- Synopsys · 35 open roles · median 38 d
- AMD · 27 open roles · median 44 d
- Cadence Design Systems · 21 open roles · median 139 d
- Qualcomm · 21 open roles · median 68 d
- Micron Technology · 14 open roles · median 41 d
- Apple · 9 open roles · median 27 d
How we counted: 244 open High-Speed IO/SerDes Design (Serdes Highspeed) roles from 47 employers tracked in the SemiconductorJobs index, counted 26 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Analog & Mixed-Signal family row. Figures refresh nightly.
Samsung Semiconductor
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