Principal Engineer, Serdes Analog Design - San Jose, California, United States
$189,000 USD yearly
Originally posted 21 January 2026 by the employer — open 232 days.
This role focuses on SerDes IPs for display interface, camera sensor interface, UCIe / die-to-die interconnect and 224/448Gbps UA-link/Ethernet.
About the role
This role involves actively working on the architecture and circuits of high-speed interconnect transceivers (Serdes) and supervising designers for complete design, silicon validation, and debugging. You will develop high-performance and low-power SerDes, including display interface, camera sensor interface, UCIe / die-to-die interconnect and 224/448Gbps UA-link/Ethernet.
What you'll do
- Define architecture and circuits for Serdes projects.
- Supervise designers to complete projects and conduct silicon validation.
- Perform hands-on circuit design.
- Translate component design specifications to schematics and build simulation test-benches.
- Evaluate circuit performance, functionality, power consumption, and reliability.
- Supervise layout of the complete project and optimize layout for power consumption and performance.
What you'll need
- Bachelors with 20+ years, Masters with 18+ years or PhDs with 15+ years of experience.
- Minimum 7+ years of experience in Analog/Serdes SoC design.
- Knowledge and experience with analog circuits/mixed signal circuits: bandgap, LDO, filters.
- Knowledge and experience with circuits of Serdes IPs: CTLE, DFE, FFE, clock distributions, PI, IQ generation.
- Knowledge of Serdes architecture and high-speed interconnect standard (USB, PCIe, UCIe).
- Well-versed in EDA tools (Cadence, Spectre, Totem, EMX).
- Comfortable with scripting languages (Python, Matlab).
Skills: SerDes, high-speed interconnect, transceiver, analog design, circuit architecture
This role has been open 165 days — well above the 91-day median for High-Speed IO/SerDes Design roles.
High-Speed IO/SerDes Design · Serdes Highspeed
|
Open roles in category
217
|
Median days open
91 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Samsung Semiconductor | All employers we track in this specialty (217 roles · 44 employers) |
|---|---|---|
| Open roles in category | 4 | 217 |
| Median days open | 114 d | 91 d (+23 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: SerDes, high-speed interconnect, transceiver, analog design, circuit architecture
Who's hiring in this category
- AMD · 24 open roles · median 61 d
- Cadence Design Systems · 19 open roles · median 153 d
- Qualcomm · 17 open roles · median 74 d
- Synopsys · 16 open roles · median 53 d
- Broadcom · 11 open roles · median 142 d
- NVIDIA · 10 open roles · median 95 d
How we counted: 217 open High-Speed IO/SerDes Design (Serdes Highspeed) roles from 44 employers tracked in the SemiconductorJobs index, counted 10 Sept 2026. Figures refresh nightly.