Principal Engineer, Post-silicon Validation
$200,000 - $255,000 USD yearly
About the role
You will lead the silicon validation of optical chiplets from initial silicon power-on through block and chip level signoff. The focus includes high-speed SerDes, photonic systems, and post-silicon validation for electronic-photonic SoCs.
What you'll do
- Define and implement validation methodologies for electronic-photonic SoCs, covering initial bringup, functional validation, electrical characterization, and system-level testing.
- Lead first silicon power-on and bringup for new tape-outs in collaboration with firmware and design teams.
- Execute post-silicon validation of SerDes interfaces, optical control loops, and mixed-signal blocks using lab equipment including BERT, DCA, oscilloscopes, OSA, and VNA.
- Apply industry standards (IEEE, OIF, JEDEC, Ethernet/Optical MSA specs) to establish validation targets, coverage objectives, and signoff criteria.
- Investigate and drive root-cause closure for silicon failure modes, including signal integrity issues and mixed-signal anomalies.
- Provide technical leadership and mentorship to validation engineers and deliver validation reports and signoff packages.
What you'll need
- Bachelor's degree in Electrical Engineering or related field with 10+ years of relevant industry experience, or Master's degree with 7+ years of experience.
- Demonstrated leadership in post-silicon validation for complex SoCs or multi-chip packages, including first silicon bringup and full signoff.
- Hands-on expertise with high-speed SerDes validation and characterization (NRZ and PAM-4) using equipment such as BERTs, oscilloscopes/DCAs, and network analyzers.
- Strong proficiency in Python for lab automation, data analysis, and test infrastructure development.
- Experience developing and owning validation test plans end-to-end.
- Deep understanding of communication protocols and standards, including Ethernet and PCIe.
Nice to have
- MSEE or equivalent.
- Familiarity with optical transceiver standards and co-packaged optics integration challenges.
- Knowledge of high-speed standards: Ethernet (200G/400G/800G), PCIe Gen5/6, and OIF CEI.
- Experience driving NPI and transition from lab validation to manufacturing test.
More semiconductor jobs: Post-silicon validation jobs · San Jose jobs
This role has been open 156 days — well above the 124-day median for Silicon Test Engineering roles.
Silicon Test Engineering · Silicon Validation
|
Open roles in category
165
|
Median days open
124 d
|
Category median salary (all employers)
$138k
|
See the full market breakdown ▾Category comparison, and who else is hiring
| Metric | Ayar Labs | All employers we track in this specialty (165 roles · 54 employers) |
|---|---|---|
| Open roles in this specialty | 2 | 165 |
| Open roles in the wider Silicon Validation & Test family | 13 | 2395 · 121 employers |
| Median days open | 156 d | 124 d (+32 d vs this employer) |
| Median salary (USD postings) | — | $138k |
Who's hiring in this category
- Infineon Technologies · 11 open roles · median 111 d
- Qualcomm · 10 open roles · median 120 d
- Renesas Electronics · 10 open roles · median 118 d
- Marvell Technology · 9 open roles · median 136 d
- Teradyne · 9 open roles · median 139 d
- Texas Instruments · 8 open roles · median 119 d
How we counted: 165 open Silicon Test Engineering (Silicon Validation) roles from 54 employers tracked in the SemiconductorJobs index, counted 8 Nov 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Silicon Validation & Test family row. Figures refresh nightly.