Principal Engineer, Mixed Signal Design Engineering - TX, Dallas, Tollway, United States
$185,125 - $250,920 USD yearly
Originally posted 12 August 2026 by the employer.
About the role
This role involves the full ownership of complex analog and mixed-signal circuit blocks for automotive high-speed SerDes products, from concept to mass production.
What you'll do
- Own complex analog and mixed-signal circuit blocks in automotive high-speed SerDes products.
- Design, simulate, and verify high-performance SerDes circuits, including advanced receiver equalizers (CTLE/FFE/DFE), CDR loops, high-speed current-mode drivers, and clock-generation circuits.
- Define architecture and develop specifications for individual blocks and system-level signal chains involving NRZ, PAM-4, and PAM-8 modulation schemes.
- Supervise physical design, including layout reviews, parasitic-aware optimization, EM-extraction, and full post-layout verification in high-frequency environments.
- Validate, characterize, and debug mixed-signal SoCs through bench evaluation, automated measurement scripts, and root-cause analysis.
- Collaborate with digital design, verification, systems, packaging, PCB, test engineering, and manufacturing teams.
What you'll need
- Master’s degree in Electronic Engineering, Electrical Engineering, or a closely related technical discipline and five (5) years of experience in analog and mixed-signal IC design.
- Demonstrated experience in high-speed analog and mixed circuit design and simulation, including SerDes-related circuits such as equalizers, CDR circuits, transmitters, and clock generation circuits.
- Demonstrated experience designing integrated circuits in CMOS process technologies, with understanding of device behavior, layout considerations, and reliability impacts.
- Demonstrated experience in transistor-level circuit analysis, including small-signal and large-signal analysis, noise, linearity, jitter, metastability, and high-frequency effects.
- Demonstrated experience in post-silicon debug and characterization of mixed-signal integrated circuits using laboratory measurement equipment and automated test setups.
- Demonstrated experience working with package, board, and layout parasitics and their impact on high-speed signal integrity, including electromagnetic simulation of passive structures.
- Demonstrated experience in Electrostatic Discharge (ESD)-aware high-speed circuit design, including industry ESD standards, device-level modeling, and transient simulation.
Skills: SerDes, equalizers, CDR loops, high-speed current-mode drivers, PAM-4
This role has been open 48 days — well below the 76-day median for High-Speed IO/SerDes Design roles.
High-Speed IO/SerDes Design · Serdes Highspeed
|
Open roles in category
239
|
Median days open
76 d
|
Median salary
$177k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Analog Devices | All employers we track in this specialty (239 roles · 49 employers) |
|---|---|---|
| Open roles in this specialty | 5 | 239 |
| Open roles in the wider Analog & Mixed-Signal family | 93 | 1385 · 107 employers |
| Median days open | 76 d | 76 d (same as this employer) |
| Median salary (USD postings) | — | $177k |
Skills observed across this category: SerDes, equalizers, CDR loops, high-speed current-mode drivers, PAM-4
Who's hiring in this category
- AMD · 28 open roles · median 64 d
- Synopsys · 26 open roles · median 44 d
- Qualcomm · 20 open roles · median 58 d
- Cadence Design Systems · 18 open roles · median 181 d
- Apple · 12 open roles · median 7 d
- NVIDIA · 11 open roles · median 116 d
How we counted: 239 open High-Speed IO/SerDes Design (Serdes Highspeed) roles from 49 employers tracked in the SemiconductorJobs index, counted 30 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Analog & Mixed-Signal family row. Figures refresh nightly.