Principal Engineer, IO Design - Boise, ID - Main Site, United States
Originally posted 31 July 2026 by the employer.
About the role
This role involves the development, design, optimization, and verification of high-speed IO and clocking circuits for DRAM related memory products. The position focuses on pushing speed limits and analyzing impairments for DRAM system and timing budgets.
What you'll do
- Innovate, design, optimize, and verify high-speed IO and clocking circuits for new DRAM products.
- Apply high-speed circuit design techniques and enhance critical performance evaluation of IO data paths and clocking paths.
- Develop accurate modeling, analysis, and simulation methodology to capture key circuit performance metrics.
- Compare silicon performance with simulation results and support correlation activities with Product Engineering and SI teams.
- Collaborate with process integration and transistor modeling teams on process node development.
What you'll need
- MSEE + 10 years or BSEE + 12 years of industry experience in analog and mixed-signal circuit design.
- Proficiency with UNIX and CADENCE design environment (simulation, schematic entry, SPF extraction).
- Understanding of device physics and basic CMOS processing techniques.
- Ability to supervise layout work and understand good layout practices for high-speed circuits.
Nice to have
- 7+ years of experience in high-speed transmitter, receiver, and clocking circuit design and optimization with proven silicon successes.
- Prior experience in channel modeling and characterization, transceiver noise and timing budget analysis, and equalization techniques.
- Demonstrated ability with AI/ML usage and fluency in scripting languages such as PERL/Python.
Skills: high-speed IO, clocking circuits, DRAM products, transmitter, receiver, channel modeling
This role has been open 60 days — well below the 76-day median for High-Speed IO/SerDes Design roles.
High-Speed IO/SerDes Design · Serdes Highspeed
|
Open roles in category
239
|
Median days open
76 d
|
Median salary
$177k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Micron Technology | All employers we track in this specialty (239 roles · 49 employers) |
|---|---|---|
| Open roles in this specialty | 10 | 239 |
| Open roles in the wider Analog & Mixed-Signal family | 48 | 1385 · 107 employers |
| Median days open | 68 d | 76 d (−8 d vs this employer) |
| Median salary (USD postings) | — | $177k |
Skills observed across this category: high-speed IO, clocking circuits, DRAM products, transmitter, receiver, channel modeling
Who's hiring in this category
- AMD · 28 open roles · median 64 d
- Synopsys · 26 open roles · median 44 d
- Qualcomm · 20 open roles · median 58 d
- Cadence Design Systems · 18 open roles · median 181 d
- Apple · 12 open roles · median 7 d
- NVIDIA · 11 open roles · median 116 d
How we counted: 239 open High-Speed IO/SerDes Design (Serdes Highspeed) roles from 49 employers tracked in the SemiconductorJobs index, counted 30 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Analog & Mixed-Signal family row. Figures refresh nightly.