Principal Engineer, Digital Verification and Emulation
$190,000 - $250,000 USD yearly
About the role
The Principal Engineer, Digital Verification and Emulation leads verification and hardware-assisted validation for silicon photonic chip designs. This role focuses on digital verification, emulation bring-up, mixed-signal-aware verification, real-number modeling, and software-driven pre-silicon validation.
What you'll do
- Lead hardware-assisted verification and own emulator bring-up, compile/debug flows, model mapping, and runtime optimization on platforms such as Synopsys ZeBu, Cadence Palladium, or Siemens Veloce.
- Build reusable verification environments for IP blocks, subsystems, and SoC-level designs using SystemVerilog, checkers, monitors, scoreboards, transactors, memory models, and bus-functional models.
- Adapt simulation environments for emulation and acceleration, including synthesizable components, test migration, and emulator-friendly verification methodology.
- Develop, integrate, and validate real-number models, behavioral models, and mixed-signal abstraction models for analog/digital interface verification.
- Partner with firmware and software teams to execute pre-silicon workloads, diagnostics, register tests, and traffic generation on emulation platforms.
- Define and track functional coverage, code coverage, assertions, CDC/RDC-sensitive logic checks, and tape-out signoff criteria.
What you'll need
- BS in Electrical Engineering, Computer Engineering, or a related field with 12+ years of ASIC/SoC digital verification experience across IP, subsystem, or SoC-level designs.
- 6+ years of hands-on experience with hardware emulation or acceleration platforms such as Synopsys ZeBu, Cadence Palladium, or Siemens Veloce, including bring-up, debug visibility, transactors, and test migration.
- Strong SystemVerilog skills and familiarity with UVM testbench development, assertions, and verification planning through coverage and signoff closure.
- Experience with real-number models, behavioral models, or mixed-signal abstraction models for analog/digital interface verification.
- Scripting and automation proficiency using Python, Tcl, Perl, Shell, or Make for regression automation, emulation build scripts, and coverage reporting.
- Solid hardware understanding of SoC interfaces and protocols such as AMBA AXI/AHB/APB, PCIe, UCIe, Ethernet, SPI/I2C, and CDC/RDC-sensitive logic.
Skills: hardware emulation platforms, SystemVerilog, mixed-signal abstraction models, functional coverage, pre-silicon validation
More semiconductor jobs: Verification engineer jobs · San Jose jobs
This role has been open 156 days — well above the 58-day median for Design Verification roles.
Design Verification · Design Verification
|
Open roles in category
1345
|
Median days open
58 d
|
Category median salary (all employers)
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Ayar Labs | All employers we track in this specialty (1345 roles · 99 employers) |
|---|---|---|
| Open roles in this specialty | 5 | 1345 |
| Open roles in the wider Digital Design & Verification family | 10 | 3525 · 120 employers |
| Median days open | 156 d | 58 d (+98 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: hardware emulation platforms, SystemVerilog, mixed-signal abstraction models, functional coverage, pre-silicon validation
Who's hiring in this category
- Qualcomm · 117 open roles · median 52 d
- Apple · 113 open roles · median 11 d
- NVIDIA · 105 open roles · median 72 d
- AMD · 85 open roles · median 68 d
- Synopsys · 74 open roles · median 52 d
- SiFive · 57 open roles · median 66 d
How we counted: 1345 open Design Verification (Design Verification) roles from 99 employers tracked in the SemiconductorJobs index, counted 8 Nov 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.