Principal Electrical Engineer – Smart Cable Modules - Shanghai Shi, China
Originally posted 22 May 2026 by the employer — open 111 days.
About the role
This Principal Electrical Engineer role involves strategic ownership of the Smart Cable Module (SCM) hardware platform, defining the electrical architecture for active copper cable assemblies and pluggable modules in OSFP, QSFP-DD, and emerging form-factor enclosures.
What you'll do
- Define the electrical architecture for smart cable modules, including SerDes channel topology, power delivery, and thermal budgeting for 112G PAM4 and 56G NRZ designs.
- Establish and maintain internal electrical design standards, PCB layout rules, and SI/PI guidelines.
- Lead technical reviews and provide authoritative sign-off on high-speed digital designs.
- Drive schematic capture and PCB design for multi-layer modules housing SerDes retimer or DSP ASICs in OSFP/QSFP-DD enclosures.
- Own power delivery design, including multi-rail regulation, hot-plug sequencing, brownout protection, and inrush management.
- Perform analog and mixed-signal sub-circuit design, including clock distribution, oscillator selection, ESD protection, and supervisory logic.
What you'll need
- Experience defining end-to-end electrical architecture for smart cable modules.
- Expertise in SerDes channel topology, power delivery strategy, and thermal budgeting.
- Proven ability to establish electrical design standards, PCB layout rules, and SI/PI guidelines.
- Background in leading technical reviews (architecture, schematic, layout, DVT) and sign-off on high-speed digital designs.
- Experience with schematic capture and PCB design for complex multi-layer modules, specifically with SerDes retimer or DSP ASICs in OSFP/QSFP-DD enclosures.
- Knowledge of power delivery design, including multi-rail regulation, hot-plug sequencing, brownout protection, and inrush management within MSA-defined power envelopes.
- Ability to review and recommend PCB stack-up, impedance targets, via structures, and differential-pair routing rules.
- Experience defining module management hardware architecture: I2C topology, register map implementation, microcontroller selection, and diagnostic monitoring interface circuitry.
- Skills in analog and mixed-signal sub-circuit design, including clock distribution, oscillator selection, ESD protection, and supervisory logic.
Nice to have
- Experience with hardware bring-up strategies, debug plans, and acceptance test procedures for new module designs.
- Ability to oversee firmware integration testing, control-interface validation, and module diagnostic monitoring verification.
- Experience leading root-cause analysis on complex hardware failures and implementing changes.
- Experience defining and championing DFT/DFM strategies with CM and PCB fabrication partners.
- Collaboration with firmware and software teams to define initialization sequences, power management schemes, and real-time diagnostic algorithms.
- Participation in MSA and IEEE standards working groups to influence specification development.
Skills: SerDes channel topology, PCB design, signal integrity, QSFP-DD, OSFP
This role has been open 110 days — well above the 91-day median for High-Speed IO/SerDes Design roles.
High-Speed IO/SerDes Design · Serdes Highspeed
|
Open roles in category
217
|
Median days open
91 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Astera Labs | All employers we track in this specialty (217 roles · 44 employers) |
|---|---|---|
| Open roles in this specialty | 4 | 217 |
| Open roles in the wider Analog & Mixed-Signal family | 7 | 1317 · 100 employers |
| Median days open | 76 d | 91 d (−15 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: SerDes channel topology, PCB design, signal integrity, QSFP-DD, OSFP
Who's hiring in this category
- AMD · 24 open roles · median 61 d
- Cadence Design Systems · 19 open roles · median 153 d
- Qualcomm · 17 open roles · median 74 d
- Synopsys · 16 open roles · median 53 d
- Broadcom · 11 open roles · median 142 d
- NVIDIA · 10 open roles · median 95 d
How we counted: 217 open High-Speed IO/SerDes Design (Serdes Highspeed) roles from 44 employers tracked in the SemiconductorJobs index, counted 10 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Analog & Mixed-Signal family row. Figures refresh nightly.