$122,900 - $255,200 USD yearly
About the role
As a Principal ASIC Engineer, you will own the full-flow ASIC development lifecycle from initial architectural concepts and RTL design down to physical sign-off and silicon bring-up.
What you'll do
- Define, establish, and optimize ASIC design methodologies and full-flow architectures across Architecture, RTL Design, Verification, and Physical Design domains.
- Translate system-level product requirements into functional SoC/ASIC microarchitectures and author synthesizable SystemVerilog/Verilog code.
- Guide engineering trade-offs evaluating Power, Performance, and Area (PPA), and collaborate with DV teams on test plans and DFT structures.
- Drive chip-level and block-level execution across synthesis, floorplanning, CTS, and automated Place & Route (P&R).
- Formulate timing constraints, execute Static Timing Analysis (STA) for setup/hold closure, and oversee physical verification including DRC, LVS, and ERC checks.
- Support silicon bring-up, hardware debugging, and lab evaluation through tape-out and commercial release.
What you'll need
- Bachelor’s degree in Electrical Engineering.
- 12+ years of direct industry experience in digital ASIC design and implementation with multiple successful commercial tape-outs.
- Mastery of SystemVerilog and Verilog for hardware design.
- Comprehensive hands-on command of the full RTL-to-GDSII flow, including logic synthesis, floorplanning, CTS, P&R, STA, and physical verification.
- Proficiency with EDA toolsuites from Synopsys (Design Compiler, IC Compiler II, PrimeTime) or Cadence (Genus, Innovus, Tempus).
- Scripting and automation proficiency in Python, TCL, and Bash/Perl.
- Direct experience with silicon bring-up, hardware debugging, and lab evaluation.
Nice to have
- Master’s or PhD degree in Electrical Engineering.
- Prior experience with Power Management ICs.
Skills: SystemVerilog, RTL-to-GDSII, synthesis, STA, P&R
More semiconductor jobs: RTL design jobs
This role has been open 5 days — well below the 64-day median for Digital/RTL Design roles.
Digital/RTL Design · RTL Design
|
Open roles in category
1096
|
Median days open
64 d
|
Category median salary (all employers)
$189k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Skyworks | All employers we track in this specialty (1096 roles · 104 employers) |
|---|---|---|
| Open roles in this specialty | 4 | 1096 |
| Open roles in the wider Digital Design & Verification family | 14 | 3525 · 120 employers |
| Median days open | 39 d | 64 d (−25 d vs this employer) |
| Median salary (USD postings) | — | $189k |
Skills observed across this category: SystemVerilog, RTL-to-GDSII, synthesis, STA, P&R
Who's hiring in this category
- Qualcomm · 139 open roles · median 73 d
- AMD · 94 open roles · median 50 d
- Synopsys · 90 open roles · median 51 d
- NVIDIA · 47 open roles · median 64 d
- NXP Semiconductors · 45 open roles · median 107 d
- Analog Devices · 41 open roles · median 54 d
How we counted: 1096 open Digital/RTL Design (RTL Design) roles from 104 employers tracked in the SemiconductorJobs index, counted 8 Nov 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.