Principal Digital Design Engineer

About the role

Navitas Semiconductor is seeking a Principal Digital Design Engineer to design and implement digital blocks for ASICs using Verilog and SystemVerilog. The role focuses on developing digital control logic and mixed-signal verification for GaN and SiC power management applications.

What you'll do

• Design and implement digital blocks for ASICs using Verilog/SystemVerilog, owning digital architecture specifications from product requirements through tape-out.
• Develop and maintain UVM/SystemVerilog testbenches, including functional coverage models, SystemVerilog Assertions (SVA), constrained-random stimulus, and formal verification.
• Build mixed-signal verification environments using real-number modeling or AMS co-simulation to verify digital-analog interactions with analog/mixed-signal blocks.
• Support ASIC tape-out execution, including synthesis, static timing analysis (STA), and design signoff.
• Develop FPGA-based test builds using Xilinx tools to validate, characterize, and debug fabricated PMIC silicon.
• Write and maintain automation scripts in Python, Tcl, and Bash for regression testing, build flows, and hardware validation.

What you'll need

• B.S. in Electrical Engineering, Computer Engineering, or a related field.
• 5+ years of industry experience in digital hardware design across ASIC, FPGA, or embedded hardware.
• Significant experience with SystemVerilog for design & verification, including metric-driven verification (code, branch, toggle, FSM, and functional coverage) and assertions.
• Solid understanding of ASIC design flows including RTL design, synthesis, timing closure, and verification.
• Experience with digital simulation tools such as Xcelium, Questa, or Vivado Simulator.
• Experience with FPGA development using Xilinx tools (Vivado, ISE) for prototyping and silicon validation, alongside scripting skills in Python, TCL, or Bash.

Nice to have

• M.S. or Ph.D. in Electrical Engineering, Computer Engineering, or a related field with 8+ years of industry experience.
• Experience designing digital circuits for PMICs, DC-DC converters, battery management, or other power management products.
• Experience with place and route (floorplanning, placement, clock tree synthesis, routing, and timing closure), static timing analysis across corners/modes, and logical equivalence checking.
• Hands-on experience with standard cell logical synthesis and writing/refining SDC constraints.
• Experience with DFT insertion, ATPG, CDC analysis, lint signoff tools, and supporting ATE test bring-up.
• Multiple successful tape-outs on mature mixed-signal or BCD processes.

More semiconductor jobs: RTL design jobs