$180,000 - $225,000 USD yearly
Own end-to-end verification for major subsystems of the Reconfigurable Dataflow Unit (RDU) using SystemVerilog and UVM.
Originally posted 13 November 2026 by the employer.
About the role
SambaNova Systems is looking for a Principal Design Verification Engineer to own verification for a major subsystem of the Reconfigurable Dataflow Unit (RDU). You will define test plans, testbench architecture, coverage models, and formal verification through tape-out sign-off.
What you'll do
- Define and own the verification execution plan end-to-end for a major subsystem of the RDU, including test plans, testbench architecture, coverage models, formal verification, and sign-off criteria.
- Build testbench components, agents, checkers, and stimulus across block, full-chip, system, and gate levels.
- Verify functional and performance behavior while establishing coverage metrics and driving closure ahead of tape-out.
- Own regression health and failure triage, leading root-cause debug on complex and intermittent pre-silicon failures.
- Advance verification methodology through reusable infrastructure, verification IP integration, and AI-assisted verification workflows.
- Contribute to emulation, FPGA prototyping, silicon bring-up, and post-silicon lab debug.
What you'll need
- BS or MS in EE, CS, or CE with 7+ years of industry experience in ASIC design verification.
- Deep hands-on expertise in SystemVerilog and SVA with standard methodologies (UVM, OVM, or VMM), plus scripting in Python and C/C++.
- Full-cycle DV ownership from test plan through tape-out on at least one complex ASIC or major subsystem, including driving a coverage model to closure.
- Experience verifying digital logic in a CPU, GPU, SoC, or comparably complex ASIC.
- Demonstrated track record of debugging hard, intermittent, or low-reproducibility pre-silicon failures to root cause.
- Working knowledge of modern computer architecture and machine learning accelerators or SoCs.
Nice to have
- MS or PhD in EE, CS, or CE with 10+ years of experience in ASIC design verification.
- Protocol-level verification experience with high-speed I/O (PCIe or Ethernet) and memory subsystems (HBM or DDR).
- Experience with performance verification methodology, formal verification, and assertion-based methods.
- Experience evaluating, integrating, and validating third-party verification IP, as well as gate-level simulation.
- Background supporting emulation platforms, FPGA prototyping, and post-silicon lab bring-up.
- Fluency applying Claude or other AI tools to verification and flow development.
Skills: SystemVerilog, UVM, SVA, testbench, coverage model, formal verification
More semiconductor jobs: SambaNova jobs · Verification engineer jobs · San Jose jobs
First seen in our index 0 days ago, well below the 59-day median for Design Verification roles.
Design Verification · Design Verification
|
Open roles in category
1395
|
Median days since first seen
59 d
|
Category median salary (all employers)
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | SambaNova | All employers we track in this specialty (1395 roles · 100 employers) |
|---|---|---|
| Open roles in this specialty | 4 | 1395 |
| Open roles in the wider Digital Design & Verification family | 8 | 3615 · 122 employers |
| Median days since first seen | 51 d | 59 d (+8 d vs this employer) |
| Median salary (USD postings) | n/a | $185k |
Skills observed across this category: SystemVerilog, UVM, SVA, testbench, coverage model, formal verification
Who's hiring in this category
- Qualcomm · 129 open roles · median 52 d
- NVIDIA · 109 open roles · median 73 d
- Apple · 107 open roles · median 16 d
- AMD · 82 open roles · median 63 d
- Synopsys · 80 open roles · median 57 d
- SiFive · 57 open roles · median 71 d
How we counted: 1395 open Design Verification (Design Verification) roles from 100 employers tracked in the SemiconductorJobs index, counted 13 Nov 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there, and is counted in the wider Digital Design & Verification family row. Days are counted from when our index first saw each posting, not from the employer's original posting date.