Principal Design Verification Engineer- SerDes/PHY IP - San Jose, California, United States
$207,000 - $230,000 USD yearly
Originally posted 27 October 2026 by the employer.
About the role
Astera Labs is hiring a Principal Design Verification Engineer to own functional verification of high-speed SerDes/PHY IP. The position focuses on verifying multi-Gbps SerDes blocks across protocols including UALink, UCIe, PCIe Gen 6/Gen 7, and Ethernet.
What you'll do
- Architect UVM-based verification environments for SerDes/PHY IP, covering PMA, PCS, and PHY-MAC interface layers. - Define verification plans, coverage models, and sign-off criteria for high-speed serial link blocks. - Develop SystemVerilog/UVM testbenches, sequences, scoreboards, and reference models for multi-Gbps SerDes lanes. - Verify PHY behavior against specifications including PCIe Gen 6/Gen 7, UALink, UCIe, and Ethernet PHY standards. - Partner with analog and mixed-signal designers on Real Number Modeling (RNM) and behavioral models. - Lead coverage analysis, debug failures with design teams, and drive regressions to tape-out.
What you'll need
- Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field. - 8+ years of design verification experience on high-speed SerDes, PHY, or mixed-signal IP. - Expert-level proficiency in SystemVerilog and UVM. - Hands-on experience with analog/mixed-signal co-simulation and Real Number Modeling (RNM). - Strong understanding of the physical layer, including equalization (CTLE, DFE, FFE), CDR, training sequences, and link bring-up. - Working knowledge of one or more high-speed serial protocols: PCIe, UALink, UCIe, Ethernet, or CXL.
Nice to have
- MS or PhD in Electrical Engineering or Computer Engineering. - Experience verifying PCIe Gen 6/Gen 7, UALink, or UCIe SerDes/PHY IP. - Familiarity with emulation platforms (Palladium, Veloce, or ZeBu) and gate-level simulation flows. - Scripting proficiency in Python or Perl for verification automation and regression management. - Experience supporting post-silicon bring-up and correlating pre-silicon coverage with silicon results.
Skills: UVM, SystemVerilog, SerDes, PCIe, RNM, coverage closure
This role has been open 0 days — well below the 67-day median for Design Verification roles.
Design Verification · Design Verification
|
Open roles in category
1268
|
Median days open
67 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Astera Labs | All employers we track in this specialty (1268 roles · 96 employers) |
|---|---|---|
| Open roles in this specialty | 18 | 1268 |
| Open roles in the wider Digital Design & Verification family | 60 | 3359 · 116 employers |
| Median days open | 73 d | 67 d (+6 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: UVM, SystemVerilog, SerDes, PCIe, RNM, coverage closure
Who's hiring in this category
- Qualcomm · 120 open roles · median 46 d
- NVIDIA · 93 open roles · median 66 d
- AMD · 92 open roles · median 56 d
- Synopsys · 67 open roles · median 42 d
- SiFive · 56 open roles · median 80 d
- Cadence Design Systems · 50 open roles · median 132 d
How we counted: 1268 open Design Verification (Design Verification) roles from 96 employers tracked in the SemiconductorJobs index, counted 27 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.