Principal Design Verification Engineer (AI Fabric Switches)
$185,000 - $240,000 USD yearly
Originally posted 8 November 2026 by the employer.
About the role
As a Principal Design Verification Engineer, you will own the full life cycle of functional verification for complex ASICs, from planning and writing tests to debugging, collecting, and closing coverage. You will also collaborate with software and system validation teams to develop test plans and execute them in emulation platforms.
What you'll do
- Execute the full life cycle of verification, including planning, test writing, debugging, and coverage collection and closure.
- Develop test-plans and test-sequences to generate stimuli, collaborating with RTL designers to debug failures.
- Deploy hybrid verification techniques utilizing both directed and constrained random approaches.
- Identify and write coverage measures for stimulus and corner-cases, closing coverage holes to ensure high-quality tape-out.
- Partner with software and system validation teams to create and execute test plans on emulation platforms.
What you'll need
- Bachelor’s degree in Electrical Engineering (EE) at minimum.
- 8 or more years of experience verifying and validating complex SoC designs for Server, Storage, and Networking applications.
- Experience with the full verification lifecycle based on SystemVerilog, UVM, C, and C++.
- Proven experience deploying both directed and constrained random verification methodologies.
- Experience defining coverage measures, bug hunting, and closing coverage for high-quality tape-out.
- Knowledge of industry-standard simulators, revision control systems, and regression systems.
Nice to have
- Master’s degree in Electrical Engineering.
- Experience with scripting tools such as Perl or Python to automate verification infrastructure.
- Prior experience using 3rd party Verification IPs for communication protocols such as PCI-Express (Gen-3 and above), Ethernet, InfiniBand, DDR4/5, NVMe, or USB.
- Experience with directed test based methodologies, cache verification, and formal methods.
Skills: SystemVerilog, UVM, Coverage Closure, Constrained Random, ASIC Verification
More semiconductor jobs: Astera Labs jobs · Verification engineer jobs · San Jose jobs
This role has been open 0 days — well below the 58-day median for Design Verification roles.
Design Verification · Design Verification
|
Open roles in category
1345
|
Median days open
58 d
|
Category median salary (all employers)
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Astera Labs | All employers we track in this specialty (1345 roles · 99 employers) |
|---|---|---|
| Open roles in this specialty | 20 | 1345 |
| Open roles in the wider Digital Design & Verification family | 62 | 3525 · 120 employers |
| Median days open | 53 d | 58 d (−5 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: SystemVerilog, UVM, Coverage Closure, Constrained Random, ASIC Verification
Who's hiring in this category
- Qualcomm · 117 open roles · median 52 d
- Apple · 113 open roles · median 11 d
- NVIDIA · 105 open roles · median 72 d
- AMD · 85 open roles · median 68 d
- Synopsys · 74 open roles · median 52 d
- SiFive · 57 open roles · median 66 d
How we counted: 1345 open Design Verification (Design Verification) roles from 99 employers tracked in the SemiconductorJobs index, counted 8 Nov 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.