Principal Design Engineer - San Jose, CA, United States
$176,000 - $298,000 USD yearly
Originally posted 7 July 2026 by the employer.
About the role
As a Principal Design Engineer in the NVE Design Engineering Core group at Micron Technology, you will contribute to the development of memory products by designing and analyzing core and mixed circuits.
What you'll do
- Serve as a technical authority in the analog/core functional team for NAND projects, participating in pathfinding activities and solving technical problems. - Collaborate on architecting NAND Xpath, Ypath, algorithms, waveforms, and drive alignment of design solutions, methodologies, DTCO, and circuits, while working across teams to evaluate and improve NAND power consumption. - Design, simulate, optimize, and floor plan NAND circuits, evaluate design feasibility, analyze circuit functionalities, and perform die size cost and benefits analysis of new array circuits and algorithms. - Implement analog and mixed-signal circuit design to meet specifications, validate performance via block and chip-level simulations using standard industry simulators, and mentor other engineers. - Develop and productize agentic enablement for circuit design, including AI/LLM-assisted flows supporting self-healing environments, guided simulation and debug, intelligent corner planning, automated schematic/layout checks, documentation synthesis, and analog/mixed-signal verification. - Partner with Product Engineering, Test, Probe, Process Integration, Assembly, and Marketing teams to optimize manufacturing functions for cost, quality, and reliability.
What you'll need
- MS in Electrical Engineering with 8+ years of relevant NAND design experience, including proficient knowledge of NAND Flash memory read, program, and erase algorithms. - Proficiency in analog/mixed-signal circuit design (page buffers, block selectors, Xdecoder, Ydecoder, bias table and waveforms, PDNs, level shifters, IO buffers, RTL, Verilog). - Strong grounding in semiconductor and device physics, analog/mixed-signal design, and semiconductor reliability issues (CHC, NBTI, stress, snapback, EM, and IR analysis). - Experience with circuit verification, optimization, layout planning, parasitic extractions, and guiding layout. - Proficiency with analog and digital simulators including HSPICE, Fast SPICE, and Verilog. - Coding skills in Python, experience working with structured data (CSV/JSON/SQLite) and version control, as well as Cadence design tools, LVS/DRC tools, and UNIX.
Nice to have
- PhD in Electrical Engineering. - Scripting experience with Bash or Tcl.
Skills: NAND circuit development, design automation, agentic circuit-design enablement, Python-based automation frameworks, EDA tools, AI/LLM-assisted flows
This role has been open 170 days — well above the 33-day median for EDA/CAD Engineering roles.
EDA/CAD Engineering · AI EDA Design
|
Open roles in category
65
|
Median days open
33 d
|
Median salary
$205k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Micron Technology | All employers we track in this specialty (65 roles · 22 employers) |
|---|---|---|
| Open roles in this specialty | 1 | 65 |
| Open roles in the wider Physical Implementation family | 77 | 1489 · 109 employers |
| Median days open | 170 d | 33 d (+137 d vs this employer) |
| Median salary (USD postings) | — | $205k |
Skills observed across this category: NAND circuit development, design automation, agentic circuit-design enablement, Python-based automation frameworks, EDA tools, AI/LLM-assisted flows
Who's hiring in this category
- NXP Semiconductors · 12 open roles · median 73 d
- NVIDIA · 8 open roles · median 31 d
- Keysight Technologies · 7 open roles · median 25 d
- Synopsys · 6 open roles · median 8 d
- Cadence Design Systems · 5 open roles · median 78 d
- Qualcomm · 4 open roles · median 25 d
How we counted: 65 open EDA/CAD Engineering (AI EDA Design) roles from 22 employers tracked in the SemiconductorJobs index, counted 25 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Physical Implementation family row. Figures refresh nightly.