Principal Design Engineer, HBM Architecture - Richardson, TX, United States
Originally posted 28 October 2026 by the employer.
About the role
As a Principal Design Engineer, HBM Architecture, you will architect, design, and optimize high-speed data paths for High Bandwidth Memory (HBM) products. This position focuses on logic-die and core-die datapath circuitry across JEDEC and custom HBM solutions.
What you'll do
- Architect and design HBM read and write datapath across core and logic die, including alignment, buffering, timing, and control logic. - Develop high-speed, low-latency datapath circuits supporting multi-channel HBM architectures and wide internal buses. - Optimize datapath designs for bandwidth, power, area, and timing closure at advanced technology nodes. - Design and integrate data reliability features, including parity, ECC hooks, lane redundancy, and remapping mechanisms. - Drive schematic-level and RTL-level datapath implementations, including clocking, gating, and reset strategies. - Collaborate with PHY, DFT, verification, and layout teams to translate specifications into robust micro-architectures.
What you'll need
- Bachelor’s degree in Electrical Engineering, Computer Engineering, or a related field with 7+ years of relevant industry experience, or a Master’s degree with 5+ years of relevant industry experience. - 3+ years of experience in high-speed digital datapath design (memory, SerDes, or SoC datapath). - 2+ years of hands-on experience with digital schematic build, RTL, or mixed-signal datapath implementations.
Nice to have
- Understanding of HBM/DRAM architectures, including read/write data flow, timing, and multi-channel operation. - Working knowledge of layout and floorplanning considerations for high-speed datapath. - Experience with static timing analysis (STA) and timing-closure methodologies. - Familiarity with advanced process-node challenges related to signal integrity, skew control, and power optimization.
Skills: HBM, datapath, micro-architectures, timing closure, DRAM