Principal Design Engineer
$185,000 - $240,000 USD yearly
Originally posted 6 November 2026 by the employer.
About the role
Principal Design Engineers develop micro-architecture and front-end circuit implementations, including RTL, synthesis, IP integration, and block-level verification for network controllers. The role focuses on high-speed interface protocols including PCI-Express (Gen-3 and above), UALink, ESUN, and Ethernet.
What you'll do
- Own full chip or block-level digital design from architecture to GDS, driving complex designs through to production.
- Develop micro-architecture specifications and RTL implementations for front-end circuits.
- Perform logic synthesis, gate-level simulations (GLS), and support timing closure using Synopsys or Cadence tools.
- Implement and support design for test (DFT), including stuck-at and transition scan test insertion.
- Collaborate with verification teams on UVM-based design verification and IP integration.
- Lead post-silicon bring-up and silicon debug activities.
What you'll need
- Bachelor’s degree in Electrical Engineering (EE).
- 8+ years of experience developing or supporting complex SoC/silicon products for Switch ASIC, Networking applications, or Server/Storage.
- Hands-on knowledge of high-speed protocols including PCIe (Gen-3 and above), UALink, ESUN, or Ethernet.
- Front-end design expertise spanning architecture, RTL, simulations, synthesis, timing closure, GLS, and DFT.
- Proficiency with Synopsys and/or Cadence digital design tools and flows.
- Experience with small-geometry CMOS (≤28nm) design rules and processes.
- Demonstrated experience in silicon bring-up and debug.
Nice to have
- Firmware development experience with C-language.
- Scripting experience with Python or equivalent programming languages.
- Prior development or support experience for PCIe or Ethernet Switch products.
- Master’s degree in Electrical Engineering.
Skills: RTL, micro-architecture, synthesis, PCIe, timing closure, SoC
More semiconductor jobs: Astera Labs jobs · RTL design jobs · San Jose jobs
This role has been open 0 days — well below the 62-day median for Digital/RTL Design roles.
Digital/RTL Design · RTL Design
|
Open roles in category
1084
|
Median days open
62 d
|
Category median salary (all employers)
$188k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Astera Labs | All employers we track in this specialty (1084 roles · 103 employers) |
|---|---|---|
| Open roles in this specialty | 24 | 1084 |
| Open roles in the wider Digital Design & Verification family | 61 | 3523 · 120 employers |
| Median days open | 55 d | 62 d (−7 d vs this employer) |
| Median salary (USD postings) | — | $188k |
Skills observed across this category: RTL, micro-architecture, synthesis, PCIe, timing closure, SoC
Who's hiring in this category
- Qualcomm · 140 open roles · median 72 d
- Synopsys · 92 open roles · median 49 d
- AMD · 78 open roles · median 48 d
- NVIDIA · 45 open roles · median 62 d
- NXP Semiconductors · 45 open roles · median 105 d
- Analog Devices · 41 open roles · median 52 d
How we counted: 1084 open Digital/RTL Design (RTL Design) roles from 103 employers tracked in the SemiconductorJobs index, counted 6 Nov 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.