Principal Design Engineer - Bangalore, India
Originally posted 12 December 2023 by the employer — open 1003 days.
High-speed Memory PHYs
About the role
This Principal Design Engineer role involves contributing to AMS design for High-speed Memory PHYs at Cadence Design Systems.
What you'll do
- Contribute to AMS design for High-speed Memory PHYs.
- Define design micro-architecture and design hierarchy for major sub-systems like Tx, Rx, or Clocking.
- Ensure AMS design quality and adherence to schedule.
- Identify potential risks and mitigation plans for sub-systems.
- Mentor and provide technical guidance to team members.
- Contribute to AMS methodology improvements.
What you'll need
- 7+ years of Analog Mixed Signal design experience.
- Sound knowledge on AMS design techniques and circuit architecture.
- Strong experience on high-speed circuits like Tx, Rx, CTLE, Amplifiers, Samplers.
- Exposure to Serdes, DDR, HBM technologies.
- Knowledge on all aspects of Mixed Signal IP design.
- Experience on working with AMS verification and logic designers to achieve AMS circuit requirements.
- Hands-on experience on block, IP, and system level design.
Skills: AMS design, High-speed Memory PHYs, high-speed circuits, Serdes, DDR, HBM technologies, AMS verification
This role has been open 169 days — well above the 91-day median for High-Speed IO/SerDes Design roles.
High-Speed IO/SerDes Design · Serdes Highspeed
|
Open roles in category
217
|
Median days open
91 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Cadence Design Systems | All employers we track in this specialty (217 roles · 44 employers) |
|---|---|---|
| Open roles in category | 19 | 217 |
| Median days open | 153 d | 91 d (+62 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: AMS design, High-speed Memory PHYs, high-speed circuits, Serdes, DDR, HBM technologies, AMS verification
Who's hiring in this category
- AMD · 24 open roles · median 61 d
- Cadence Design Systems (this employer) · 19 open roles · median 153 d
- Qualcomm · 17 open roles · median 74 d
- Synopsys · 16 open roles · median 53 d
- Broadcom · 11 open roles · median 142 d
- NVIDIA · 10 open roles · median 95 d
How we counted: 217 open High-Speed IO/SerDes Design (Serdes Highspeed) roles from 44 employers tracked in the SemiconductorJobs index, counted 10 Sept 2026. Figures refresh nightly.