Principal Design Engineer - Bangalore, India
Originally posted 6 February 2026 by the employer — open 216 days.
Join a team developing high-performance physical IP for industry-standard protocols.
About the role
This role involves developing high-performance physical IP for industry-standard protocols, contributing to the digital architecture, RTL, low power design, synthesis, and timing analysis for the SerDes physical IP portfolio.
What you'll do
- Contribute to digital architecture, digital RTL, low power design, synthesis and timing analysis, and behavioral coding for IPs.
- Execute various tool flows for IP quality control.
- Drive architecture to micro-architecture to RTL implementation with refining of features/requirements.
- Work with the verification team to specify coverage points, testing strategy, corner conditions and stimulus creation.
- Debug verification test cases / SVA's to cover the design.
What you'll need
- 7+ Years’ experience in Digital Design and Architecture.
- Proven experience in Design Architecture.
- Proven experience in Design implementation.
- Proven experience in Embedded uC Designs.
- Proven experience in Synthesis and SDC Creation.
- Proven experience in Scripting of design automation.
- Knowledge of existing Serial standards such as PCIE, USB, Ethernet.
Nice to have
- Knowledge of System Verilog, Python, C/C++.
- Working knowledge of revision control tools such as Perforce, Git, SVN.
Skills: physical IP, SerDes, digital architecture, RTL, low power design, synthesis, timing analysis
This role has been open 169 days — well above the 91-day median for High-Speed IO/SerDes Design roles.
High-Speed IO/SerDes Design · Serdes Highspeed
|
Open roles in category
217
|
Median days open
91 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Cadence Design Systems | All employers we track in this specialty (217 roles · 44 employers) |
|---|---|---|
| Open roles in category | 19 | 217 |
| Median days open | 153 d | 91 d (+62 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: physical IP, SerDes, digital architecture, RTL, low power design, synthesis
Who's hiring in this category
- AMD · 24 open roles · median 61 d
- Cadence Design Systems (this employer) · 19 open roles · median 153 d
- Qualcomm · 17 open roles · median 74 d
- Synopsys · 16 open roles · median 53 d
- Broadcom · 11 open roles · median 142 d
- NVIDIA · 10 open roles · median 95 d
How we counted: 217 open High-Speed IO/SerDes Design (Serdes Highspeed) roles from 44 employers tracked in the SemiconductorJobs index, counted 10 Sept 2026. Figures refresh nightly.