Principal CPU Physical Design Engineer (San Diego, CA)
$211,900 - $317,900 USD yearly
Originally posted 10 June 2026 by the employer.
About the role
This role involves owning critical portions of CPU implementation from RTL to GDS, focusing on PPA convergence, design quality, and physical implementation at advanced nodes.
What you'll do
- Own critical portions of CPU implementation from RTL to GDS, focusing on PPA convergence and design quality. - Drive timing, power, and area optimization for high-frequency CPU subsystems. - Partner with Architecture, RTL, and Circuit teams to co-optimize designs for physical implementation. - Address silicon challenges including timing closure, congestion, variability, EM/IR, and power integrity. - Develop and deploy methodologies, flows, and automation to improve scalability and QoR across projects. - Collaborate with EDA vendors and CAD teams while mentoring junior engineers.
What you'll need
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field with 8+ years of relevant hardware engineering experience (or Master's degree with 7+ years, or PhD with 6+ years). - 10 years of experience in ASIC/SoC Physical Design. - Strong experience with full RTL-to-GDSII implementation, including synthesis, place & route, STA, and signoff. - Experience in timing closure and power optimization. - Scripting skills in TCL, Python, or similar languages.
Nice to have
- Experience working on CPU cores or other high-performance designs. - Expertise in advanced nodes (7nm, 5nm, 3nm or below). - Strong understanding of PPA trade-offs and CPU-specific design challenges. - Hands-on experience with industry-standard tools (Synopsys/Cadence). - Experience developing or influencing design methodologies.
Skills: RTL to GDS, PPA convergence, timing closure, place & route, advanced nodes
This role has been open 135 days — well above the 63-day median for Physical Design roles.
Physical Design · Physical Design
|
Open roles in category
673
|
Median days open
63 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Qualcomm | All employers we track in this specialty (673 roles · 79 employers) |
|---|---|---|
| Open roles in this specialty | 123 | 673 |
| Open roles in the wider Physical Implementation family | 169 | 1494 · 109 employers |
| Median days open | 46 d | 63 d (−17 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: RTL to GDS, PPA convergence, timing closure, place & route, advanced nodes
Who's hiring in this category
- Qualcomm (this employer) · 122 open roles · median 46 d
- AMD · 63 open roles · median 27 d
- Intel Corporation · 40 open roles · median 15 d
- NVIDIA · 38 open roles · median 68 d
- Synopsys · 37 open roles · median 37 d
- Broadcom · 34 open roles · median 102 d
How we counted: 673 open Physical Design (Physical Design) roles from 79 employers tracked in the SemiconductorJobs index, counted 23 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Physical Implementation family row. Figures refresh nightly.