Principal ASIC Verification Engineer
About the role
As a Principal ASIC Verification Engineer, you will be responsible for the verification closure of entire projects, including design modules, sub-systems, and SoCs, specifically for high performance computing, high performance data analytics, and artificial intelligence interconnect solutions.
What you'll do
- Define overall SoC level verification strategy, technical planning, and direction.
- Drive the development of UVM environments to verify RTL at block, unit, and SoC levels.
- Develop and execute functional tests according to verification test plans.
- Instrument testbenches for functional and code coverage and drive to closure based on coverage metrics.
- Collaborate with cross-functional teams like design, software, emulation, and silicon validation to ensure design quality.
- Provide day-to-day guidance and leadership to team members.
What you'll need
- 15+ years of experience with hands-on coding using UVM/System Verilog.
- Experience with verification for complex SoCs that include multiple clock and reset domains, using VCS or equivalent simulation tools.
- Experience debugging failures to the line of RTL, closing out bug fixes, using Verdi or equivalent debug tools.
- Experience in ground-up testbench development.
- Experience with revision control systems like Git or SVN.
- B.S. Degree in Computer Engineering, Computer Science, or Electrical Engineering.
Nice to have
- M.S. Degree in Computer Engineering, Computer Science, or Electrical Engineering.
- 15+ years of relevant experience in networking hardware verification, verifying 50G, 100G, 400G Ethernet MAC/PCS protocols, TCP/IP, RDMA/RoCE, IPSec.
- Expertise in their application in high-speed data processing/networking.
- Experience with one or more scripting languages (TCL, Python, Perl, Shell-scripting).
- Track record of first-pass success in ASIC and Systems.
Skills: UVM, SystemVerilog, SoC verification, testbench, coverage closure
More semiconductor jobs: Verification engineer jobs · San Jose jobs
This role has been open 66 days — slightly above the 58-day median for Design Verification roles.
Design Verification · Design Verification
|
Open roles in category
1345
|
Median days open
58 d
|
Category median salary (all employers)
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Cornelis Networks | All employers we track in this specialty (1345 roles · 99 employers) |
|---|---|---|
| Open roles in this specialty | 3 | 1345 |
| Open roles in the wider Digital Design & Verification family | 7 | 3525 · 120 employers |
| Median days open | 66 d | 58 d (+8 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: UVM, SystemVerilog, SoC verification, testbench, coverage closure
Who's hiring in this category
- Qualcomm · 117 open roles · median 52 d
- Apple · 113 open roles · median 11 d
- NVIDIA · 105 open roles · median 72 d
- AMD · 85 open roles · median 68 d
- Synopsys · 74 open roles · median 52 d
- SiFive · 57 open roles · median 66 d
How we counted: 1345 open Design Verification (Design Verification) roles from 99 employers tracked in the SemiconductorJobs index, counted 8 Nov 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.