Principal Analog Design Engineer — Mixed-Signal PHY (Clocking / High-Speed I/O)
Analog & Mixed-Signal Design
About the role
This role involves developing custom analog circuits for innovative PHY solutions focusing on high-speed chip-to-chip and memory interconnect.
What you'll do
- Lead the development of specialized analog components, focusing on clocking (PLL, DLL, CDR) and transmitter/receiver circuits.
- Contribute to top-level PHY analog architecture decisions, including clocking topology and signal chain partitioning.
- Build and maintain transistor-level simulation testbenches; perform process corner, statistical sampling, and evaluate variations.
- Define and detail clear interface specifications between custom analog blocks and the digital control wrapper.
- Collaborate with the layout team to guide custom analog layout and support post-silicon characterization in the lab.
What you'll need
- BS, MS, or PhD in Electrical Engineering or related field, or equivalent experience.
- 10+ years of analog/mixed-signal IC build experience with at least one tape-out in a primary circuit ownership role.
- Deep expertise in clocking circuit building — PLL, DLL, or CDR architecture and transistor-level implementation in sophisticated CMOS nodes.
- Strong transistor-level simulation skills using HSpice or equivalent; comfort with corner, Monte Carlo, and mismatch analysis.
- Proven understanding of jitter analysis and its impact on high-speed link timing margins.
Nice to have
- Experience with high-speed transmitter development — output driver architectures, pre-emphasis, swing control, and impedance matching for multi-Gbps die-to-die or SerDes interfaces.
- Background in rapid receiver development — sense amplifiers, CTLE/DFE equalization, sampler development, and threshold calibration.
- Familiarity with die-to-die or chip-to-chip PHY architectures — UCIe, AIB, BoW, or proprietary short-reach interconnect standards.
- Experience working with OTP/fuse-based calibration architectures and analog trim loop implementation.
- Post-silicon characterization experience — correlating simulation results to measured eye diagrams, BER curves, phase noise plots, and jitter histograms on real hardware.