Principal Analog Circuit Design Engineer - SerDes - Virtual Canada, Canada
Analog & Mixed-Signal Design
Originally posted 19 May 2026 by the employer — open 114 days.
About the role
This role involves designing, developing, and building analog circuits in advanced process nodes for analog and mixed-signal IPs, focusing on high-speed SerDes applications.
What you'll do
- Design floorplans and perform analog circuit design.
- Extract chip parameters and simulate analog behavior models.
- Create test plans and evaluate test results to verify design according to specifications.
- Verify functionality to optimize circuit for power, performance, area, timing, and yield.
- Collaborate cross-functionally to report design progress and resolve performance and circuit design issues.
- Optimize performance, power, area, and reduce leakage of circuits.
What you'll need
- Master's degree in Electrical Engineering, Electronics Engineering, or related field.
- 8+ years of experience in analog/mixed-signal circuit design for high-speed SerDes applications.
- Expertise in one or more of the following areas: PLL, CDR, CTLE, DFE, ADC, or Transmitter (TX) design.
- Strong understanding of high-speed communication standards such as PCIe (Gen5/Gen6) and Ethernet (100G/400G/800G).
- Solid foundational knowledge of analog design principles-noise, jitter, matching, stability, and linearity.
- Hands-on experience with advanced FinFET CMOS process technologies (7nm or below).
- Proficiency in analog design and simulation tools such as Cadence Virtuoso/ADE, HSPICE, or equivalent.
- Experience in silicon bring-up, post-silicon validation, and lab debug of analog circuits.
Nice to have
- Ph.D. in Electrical Engineering, Electronics Engineering, or related field.
- 10+ years of experience in analog design for high-speed SerDes (56G/112G/224G) applications.
- Deep expertise in transmitter and receiver architecture, CDR loops, equalization techniques, and advanced ADC architectures.
- Hands-on experience in behavioral modeling (Verilog-A), MATLAB-based analysis, and automation scripting (Python/Tcl/Perl).
- Strong understanding of signal integrity, channel modeling, and system-level link performance.
- Proven ability to mentor junior engineers, guide layout implementation, and drive design reviews.
Skills: analog circuit design, mixed-signal, SerDes, PLL, CDR, CTLE, DFE, ADC, PCIe
Market context
This role has been open 131 days — well above the 91-day median for High-Speed IO/SerDes Design roles.
High-Speed IO/SerDes Design · Serdes Highspeed
|
Open roles in category
217
|
Median days open
91 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Intel Corporation | All employers we track in this specialty (217 roles · 44 employers) |
|---|---|---|
| Open roles in category | 7 | 217 |
| Median days open | 132 d | 91 d (+41 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: analog circuit design, mixed-signal, SerDes, PLL, CDR, CTLE
Who's hiring in this category
- AMD · 24 open roles · median 61 d
- Cadence Design Systems · 19 open roles · median 153 d
- Qualcomm · 17 open roles · median 74 d
- Synopsys · 16 open roles · median 53 d
- Broadcom · 11 open roles · median 142 d
- NVIDIA · 10 open roles · median 95 d
How we counted: 217 open High-Speed IO/SerDes Design (Serdes Highspeed) roles from 44 employers tracked in the SemiconductorJobs index, counted 10 Sept 2026. Figures refresh nightly.