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Astera Labs

Principal Advanced Packaging Engineer - San Jose, California, United States

Astera Labs San Jose, California, United States 21 days ago
Packaging & Advanced Integration

$205,000 - $260,000 USD yearly

Originally posted 14 September 2026 by the employer — open 0 days.

About the role

This individual contributor role focuses on leading R&D for advanced packaging technologies for optical chips. The scope includes setting technical direction and driving packaging technology development for NPO and CPO products.

What you'll do

  • Lead R&D for advanced packaging of optical chips, including 2.1D, 2.5D, and 3D integration.
  • Define and optimize wafer-level, panel-level, or die-level packaging process flows.
  • Drive EIC-to-PIC integration and broader optical device integration efforts.
  • Select and qualify packaging materials for advanced packaging.
  • Partner with OSAT, tool vendors, and material suppliers to drive equipment, process, and materials development.
  • Characterize and continuously improve yield, reliability, and process capability for NPO and CPO packages.

What you'll need

  • 8+ years of experience in semiconductor or advanced packaging engineering.
  • Deep expertise in advanced packaging processes, including 2.5D/3D integration, flip-chip, hybrid bonding, Cu pillar, TSV, RDL, and overmold across wafer-, panel-, and die-level flows.
  • Experience with silicon photonics chip packaging and EIC/PIC integration.
  • Hands-on experience with advanced packaging materials, including underfill, molding compounds, dielectrics, adhesives, or optical-grade encapsulants.
  • Proven track record of equipment and process qualification with OSAT or tool suppliers.
  • Experience with PDK development and packaging design rule authoring.
  • Strong foundation in yield analysis, reliability characterization, and process capability methodologies such as Cpk and SPC.

Nice to have

  • Hands-on experience with CPO or NPO product development.
  • Experience with optical coupling or waveguide alignment for photonic integration.
  • Familiarity with DFM and DFT for advanced packaging.
Market context

This role has been open 0 days — well below the 56-day median for Packaging Engineering roles.

Packaging Engineering · Advanced Packaging

Open roles in category
289
Median days open
56 d
Median salary
$179k
See the full market breakdown ▾Category comparison, and who else is hiring
How Astera Labs compares in Packaging Engineering hiring
Metric Astera Labs All employers we track in this specialty (289 roles · 55 employers)
Open roles in this specialty 5 289
Open roles in the wider Process, Fab & Equipment family 13 9301 · 110 employers
Median days open 23 d 56 d (−33 d vs this employer)
Median salary (USD postings) — $179k

Who's hiring in this category

  • KLA Corporation · 52 open roles · median 96 d
  • Micron Technology · 28 open roles · median 34 d
  • Infineon Technologies · 20 open roles · median 34 d
  • Renesas Electronics · 20 open roles · median 17 d
  • Intel Corporation · 16 open roles · median 58 d
  • Lumilens · 13 open roles · median 38 d

How we counted: 289 open Packaging Engineering (Advanced Packaging) roles from 55 employers tracked in the SemiconductorJobs index, counted 14 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Process, Fab & Equipment family row. Figures refresh nightly.

Apply now
San Jose, California, United States
On-site
$205,000 - $260,000 USD yearly
21 days ago

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